6402 datasheet(128/250 Pages) INTEL

128 / 250 page

DDR MemBIST

128

Intel® 6400/6402 Advanced Memory Buffer Datasheet

be determined from the sequence numbering this is a 10N

pattern.

11.3.5

Error Reporting and Control

Information about failures detected by MemBIST is reported in a variety of ways.

These are summarized here and detailed in the following sections. MBCSR:pf set

during a MemBIST operation indicates that a failure was detected. MBDATA can log the

addresses of up to 5 failures. When the MemBIST operation is utilizing a fixed data

pattern selected using MBCSR:dtype = 0x0, MBDATA also contains a failure data bit

location accumulator, which logs any data bit that has seen a failure during the

operation. With other dtypes, the failure data bit location accumulator may replace the

address logs. MB_ERR_DATA logs the first four 144-bit data words which MemBIST

detects as containing an error after the Memory Test Failure Address Pointer Register

(MBFADDRPTR) has counted down to zero. MBFADDRPTR makes it possible to extract

the failure data information for all repeatable failures which occur during execution of a

MemBIST operation.

How the available logs in are filled depends partly upon the MemBIST configuration and

partly upon how the errors detected by MemBIST occur. For example, when MemBIST

is set to halt on error and a failure is detected, MemBIST does not advance to the next

address. However, due to the architecture of the memory system, there may be more

than one error to log from the single address that was being checked when the failure

was detected. At burst length of 4, for each address there are four 72-bit bus-widths of

data to be checked. Data is logged in 144-bit quantities. If a bit in the DRAM bus was

stuck, this might result in an error being detected in each of the four 72-bit bus-widths

of data. Even though MemBIST is set to halt on error, this would result in two 144-bit

data error logs, each with a corresponding failure address log. Operating at BL=8 could

result in up to four 144-bit data error logs being written with their corresponding

address logs.

When MemBIST is not set to halt on error, logs will fill as errors occur. The logs may

contain information from several unrelated failing addresses. The first four failures to

be detected will cause the first four 144-bit failure data chunks to be logged along with

their corresponding addresses. The address of the fifth error to occur will also be

logged, although there is no location available to log the failure data. The sixth and

succeeding errors will not be logged. During execution of a MemBIST operation,

MemBIST will not overwrite a log entry that has already been filled during that

operation to record a more recent failure.

11.3.5.1

Control Register Pass/Fail Bit and Halt On Error

The MemBIST pass/fail bit, MBCSR:pf, is always cleared when MemBIST execution

starts. If a failure is ever detected, this bit is always set immediately. If MBCSR:halt

(halt on detection of read-compare error) is set, and MBCSR:pf is then set due to

detection of an error, MemBIST execution always completes the accesses to the current

address and then halts without proceeding to the next address. No other MemBIST

controls, including a non-zero value in MBFADDRPTR, modifies the setting of the failure

bit or the halting on failure detection as described.

11.3.5.2

Failure Address Logging

The addresses of the first 5 detected failures can be logged by MemBIST. The address

logs (located in MBDATA) are always cleared, and the logging pointer is always reset to

start logging with the first log, each time that MemBIST starts execution of a new

operation.

6402 Datasheet(PDF) 128 Page - Intel Corporation

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