6402 datasheet(131/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

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DDR MemBIST

To use this feature, MemBIST must be set to continue on error by clearing MBCSR:halt.

Otherwise MemBIST will halt on detecting the first failure and later failures will not be

detected or logged. Neither setting of the failure bit, nor halting on failure detection is

affected by a non-zero value in MBFADDRPTR.

The general procedure for using this feature is to run MemBIST, read and record the

address and data failure information from the logs, and then add the number of failure

logs received to the value in MBFADDRPTR to cause the failure information already

captured to be ignored on the next pass. This process is repeated until MemBIST

completes with zeros in the address logs. This indicates that no further errors were

detected beyond those already logged. (Watch the case of decrementing addressing

ending at address 0. A failure at address 0 with failure data of zero is possible.)

To generate a complete data log of all failures, use the following procedure:

1. Define starting and ending addresses, address modes and data patterns, set

MBFADDRPTR to zero, set halt on error to 0 (don’t halt on error).

2. Start MemBIST and check the result. If pass, exit. If fail, continue.

3. Read out the failing addresses and data. If the address and data logs are zero (and

the address space covered by this pass of MemBIST does not include address 0),

exit, as all failures have been seen. Otherwise, continue. (If the address space

covered by this pass of MemBIST does include address 0, and it is ambiguous

whether or not address 0 has failed, the ambiguity can be resolved by retesting

only address 0.)

4. Add the number of complete logs (for which both address and data were read)

obtained during this pass to the value in MBFADDRPTR so that these failures will

not be seen again on the next pass of MemBIST.

5. Go to step 2

11.3.6

DRAM Throttling

MemBIST can generate high DRAM bandwidth and consequently, high power

consumption and thermal stress. Although this is manageable in a dedicated test

environment, a system’s power and cooling capacity may be exceeded. For this reason

MemBIST allows insertion of deselect cycles on every address change. The deselects

will be inserted after each read or write command. This allows slowing down BIST

execution if necessary to stay within a given power or cooling envelope.

11.3.7

Refresh Control

In normal operation, refresh commands are issued by the host rather than by the AMB.

However, during MemBIST, when commands to the DRAM originate from the AMB,

refresh must be provided by MemBIST. The refresh and MemBIST state machines are

implemented as separate state machines, allowing refresh when MemBIST is not

active. The refresh interval is programmable by setting a 15 bit refresh counter. For

example, at the maximum address frequency of 400 Mhz (250 pS), 3120 clocks are

needed to achieve the nominal refresh interval of 7.8 µS. The maximum interval in this

case will be 81.9 µS. The default refresh value should be usable in most circumstances.

The refresh interval may be programmed to other values to meet special needs.

6402 Datasheet(PDF) 131 Page - Intel Corporation

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