6402 datasheet(203/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

203

Registers

14.5.3.6

TEMP: Temperature A/D

Current temperature reading. This 8-bit value with 0.5 degree of resolution is

continuously and automatically kept up to date by AMB hardware.

14.6

Implementation Specific DDR Initialization and

Calibration Registers (Function 4)

14.6.1

DDR Calibration

14.6.1.1

DCALCSR: DCAL Control and Status

Device:

NodeID

Function: 3

Offset:

85h

Bit

Attr

Default

Description

7:0

00h

DEGREES: Current temperature - binary encode 0 - 127.5 degrees C

Device:

NodeID

Function: 4

Offset:

40h

Bit

Attr

Default

Description

RWS

START: Start Operation

When set to 1 by software, the operation selected by the dcalcsr.opcode is

initiated. Hardware clears this bit when the operation is complete.

30:28

FAIL: Completion Status

1xx = Fail, 0xx = Pass

BASPAT: This controls which data pattern is used for the DQS Delay

calibration. Setting this field enables the use of the basic data pattern

selected by the DCALCSR.PATTERN bits. When cleared, the extended data

pattern specified in the DDQSCVDP and DDQSCADP registers is used.

RSTREGSS: Reset DCALDATA CSR in single step calibration mode. This bit

should be set during the first step of a single step calibration. It will enable

hardware to clear all registers and status bits during the calibration step

the same way hardware does on the first step of an automatic “all passes”

calibration.

25:24

CHSEL: This field defines bus folding. This function is obsolete and is not

supported.

SGLSTP: Single Step Calibration Operation

Applies only to Receive enable, DQS cal, and I/O loopback

“1” = Single step - a single step of the algorithm selected by the OPCODE

is run by hardware. No data analysis is run.

“0” = All passes - all steps of the algorithm selected by the OPCODE is run

by hardware including data analysis.

22:21

CS: Rank select

This field corresponds to the chip select outputs: CS[1:0]. Setting a bit in

this field will cause the corresponding CS pin to drive low when commands

are issued on the DDR bus. This field Applies to NOP, Refresh, Precharge

all, and MRS/EMRS commands. It also applies to Receive Enable, and DQS

Delay cal in single step mode.

Reserved

A0_DQSCAL: revert to A0 DQSCAL algorithm

6402 Datasheet(PDF) 203 Page - Intel Corporation

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