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6402 Datasheet(PDF) 204 Page - Intel Corporation |
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6402 Datasheet(HTML) 204 Page - Intel Corporation |
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204 / 250 page  Registers 204 Intel® 6400/6402 Advanced Memory Buffer Datasheet 14.6.1.2 DCALADDR: DCAL Address Register 18:16 RW 000 PATTERN: Basic data pattern for DQS cal and I/O loopback. This sets the burst length 4 pattern for a nibble of data. The pattern is repeated for BL8. This pattern is replicated on all nibbles of the data bus. “000” = F > 0 > F > 0 “001” = 0 > F > 0 > F “010” = A > 5 > A > 5 “011” = 5 > A > 5 > A “100” = C > 3 > C > 3 “101” = 3 > C > 3 > C “110” = 9 > 6 > 9 > 6 “111” = 6 > 9 > 6 > 9 15 RW 0 DARWPR: Disable FIFO reset in single pass mode. Applies only to Receiver enable, DQS cal, and I/O loopback. When set to 1, this bit inhibits the core to DDR cluster reset signal generated during the cal/hvm modes listed above. This prevents the DDR cluster synchronizer FIFO write pointer and data latches from being reset so that they can be read out of the cluster using the error monitor function. The reset signal can only be disabled in single step mode. When the ALLP bit is set to 1, the DARWPR bit has no effect. 14:4 RW 000h OPMODS: Operation modifiers 3:0 RW 0h OPCODE: “0000” = NOP “0001” = Refresh “0010” = Pre-Charge “0011” = MRS/EMRS “0101” = Automatic DQS Delay Calibration “1100” = Automatic Receive Enable Calibration “1101” = Self-Refresh Entry All other settings are reserved Device: NodeID Function: 4 Offset: 44h Bit Attr Default Description 31:0 RW 0000_0000h DCALADDR: DCAL Address and Other Information Based on Opcode. Device: NodeID Function: 4 Offset: 40h Bit Attr Default Description |
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