6402 datasheet(248/250 Pages) INTEL

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Glossary

248

Intel® 6400/6402 Advanced Memory Buffer Datasheet

Electromagnetic

EMI

Electromagnetic interference

FBD

Fully-Buffered DIMM

FBD Channel

Combination of 10 lane Southbound Links and 13 or 14 lane Northbound Links

that make up a logical memory channel from host perspective

FBDIMM

Fully-Buffered DIMM

FERR

First Error

FIFO

First-In, First-Out. Usually in reference to a buffer implementation.

Frame

Group of bits containing commands or data

FSM

Finite State Machine

HCSL

High-speed Current Steering Logic

Host

Memory controller agent on an FBD channel

IBIST

Interconnect Built-In Self-Test (built-in interconnect test)

I/O

Input Output. Usually in reference to a bidirectional buffer cell or circuit.

ISI

Inter Symbol Interference – see section “Initialization / Clocking” for definition

JEDEC

JEDEC Solid State Technology Association (once known as the Joint Electron

Device Engineering Council)

JESD79

JEDEC Standard 79, DDR SDRAM Specification

JTAG

Joint Test Action Group. Usually in reference to the IEEE 1149.1a boundary scan

test standard.

Logic Analyzer

LAI

Logic Analyzer Interface

Lane

Differential pair of receivers or transmitters

LFSR

Linear Feedback Shift Register. Usually in reference to pseudo-random bit-

stream data.

Link

High speed parallel Differential Point-to-Point interface

Memory interface Control (block)

MemBIST

Memory Built-In Self-Test

Mesochronous

Small ppm frequency difference.

MTBF

Mean Time Between Failures

MT/s

Mega Transfers per Second

NACK

Not-ACKnowledge. Usually in reference to SMBus communications.

Northbound

NBI

Northbound Interface. (also: Northbound link control logic)

NERR

Next/Subsequent Error

Northbound

The direction of signals running from the furthest DIMM toward the host.

ODT

On-Die Termination

Page Replace aka Page

Miss, Row Hit / Page Miss

An access to a row that has another page open. The page must be transferred

back from the sense amps to the array, and the bank must be precharged.

Page Hit

An access to an open page, or DRAM row. The data can be supplied from the

sense amps at low latency.

Page Miss (Empty Page)

An access to a page that is not buffered in sense amps and must be fetched

from DRAM array.

PEC

Packet Error Code

Plesiochronous

Having the same frequency but arbitrary phase differences.

PLL

Phase Locked Loop

Term

Definition

6402 Datasheet(PDF) 248 Page - Intel Corporation

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