641 datasheet(70/106 Pages) INTEL

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Land Listing and Signal Descriptions

Datasheet

MCERR#

Input/

Output

MCERR# (Machine Check Error) is asserted to indicate an

unrecoverable error without a bus protocol violation. It may be

driven by all processor FSB agents.

MCERR# assertion conditions are configurable at a system level.

Assertion options are defined by the following options:

• Enabled or disabled.

• Asserted, if configured, for internal errors along with IERR#.

• Asserted, if configured, by the request initiator of a bus transaction after

it observes an error.

• Asserted by any bus agent when it observes an error in a bus

transaction.

For more details regarding machine check architecture, refer to the

Intel® 64 and IA-32 Architecture Software Developer’s Manual,

Volume 3: System Programming Guide.

MSID[1:0]

Input

MSID[1:0] (input) MSID0 is used to indicate to the processor

whether the platform supports 775_VR_CONFIG_05B processors. A

775_VR_CONFIG_05B processor will only boot if it’s MSID0 pin is

electrically low. A 775_VR_CONFIG_05A processor will ignore this

input.

MSID1 must be electrically low for the processor to boot.

PROCHOT#

Input/

Output

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the

processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC) has

been activated, if enabled. As an input, assertion of PROCHOT# by

the system will activate the TCC, if enabled. The TCC will remain

active until the system de-asserts PROCHOT#. See Section 5.2.4

for more details.

PWRGOOD

Input

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and

power supplies are stable and within their specifications. ‘Clean’

implies that the signal will remain low (capable of sinking leakage

current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal must

then transition monotonically to a high state. PWRGOOD can be

driven inactive at any time, but clocks and power must again be

stable before a subsequent rising edge of PWRGOOD.

The PWRGOOD signal must be supplied to the processor; it is used

to protect internal circuits against voltage sequencing issues. It

should be driven high throughout boundary scan operation.

REQ[4:0]#

Input/

Output

REQ[4:0]# (Request Command) must connect the appropriate

pins/lands of all processor FSB agents. They are asserted by the

current bus owner to define the currently active transaction type.

These signals are source synchronous to ADSTB0#. Refer to the

AP[1:0]# signal description for a details on parity checking of these

signals.

Table 25.

Signal Description (Sheet 1 of 9)

Name

Type

Description

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