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641 Datasheet(PDF) 60 Page - Intel Corporation

Part # 641
Description  Intel Pentium 4 Processor
PDF  106 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

641 Datasheet(HTML) 60 Page - Intel Corporation

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Land Listing and Signal Descriptions
60
Datasheet
E8
VSS
Power/Other
E9
D19#
Source Synch Input/Output
F10
VSS
Power/Other
F11
D23#
Source Synch Input/Output
F12
D24#
Source Synch Input/Output
F13
VSS
Power/Other
F14
D28#
Source Synch Input/Output
F15
D30#
Source Synch Input/Output
F16
VSS
Power/Other
F17
D37#
Source Synch Input/Output
F18
D38#
Source Synch Input/Output
F19
VSS
Power/Other
F2
FC5
Common Clock
Input
F20
D41#
Source Synch Input/Output
F21
D43#
Source Synch Input/Output
F22
VSS
Power/Other
F23
RESERVED
F24
TESTHI7
Power/Other
Input
F25
TESTHI2
Power/Other
Input
F26
TESTHI0
Power/Other
Input
F27
VTT_SEL
Power/Other
Output
F28
BCLK0
Clock
Input
F29
RESERVED
F3
BR0#
Common Clock Input/Output
F4
VSS
Power/Other
F5
RS1#
Common Clock
Input
F6
IMPSEL
Power/Other
Input
F7
VSS
Power/Other
F8
D17#
Source Synch Input/Output
F9
D18#
Source Synch Input/Output
G1
VSS
Power/Other
G10
RESERVED
G11
DBI1#
Source Synch Input/Output
G12
DSTBN1#
Source Synch Input/Output
G13
D27#
Source Synch Input/Output
G14
D29#
Source Synch Input/Output
G15
D31#
Source Synch Input/Output
G16
D32#
Source Synch Input/Output
G17
D36#
Source Synch Input/Output
G18
D35#
Source Synch Input/Output
Table 24.Numerical Land Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
G19
DSTBP2#
Source Synch Input/Output
G2
FC1
Power/Other
Input
G20
DSTBN2#
Source Synch Input/Output
G21
D44#
Source Synch Input/Output
G22
D47#
Source Synch Input/Output
G23
RESET#
Common Clock
Input
G24
TESTHI6
Power/Other
Input
G25
TESTHI3
Power/Other
Input
G26
TESTHI5
Power/Other
Input
G27
TESTHI4
Power/Other
Input
G28
BCLK1
Clock
Input
G29
BSEL0
Power/Other
Output
G3
TESTHI8
Power/Other
Input
G30
BSEL2
Power/Other
Output
G4
TESTHI9
Power/Other
Input
G5
FC7
Source Synch
Output
G6
RESERVED
G7
DEFER#
Common Clock
Input
G8
BPRI#
Common Clock
Input
G9
D16#
Source Synch Input/Output
H1
GTLREF0
Power/Other
Input
H10
VSS
Power/Other
H11
VSS
Power/Other
H12
VSS
Power/Other
H13
VSS
Power/Other
H14
VSS
Power/Other
H15
DP1#
Common Clock Input/Output
H16
DP2#
Common Clock Input/Output
H17
VSS
Power/Other
H18
VSS
Power/Other
H19
VSS
Power/Other
H2
GTLREF1
Power/Other
Input
H20
VSS
Power/Other
H21
VSS
Power/Other
H22
VSS
Power/Other
H23
VSS
Power/Other
H24
VSS
Power/Other
H25
VSS
Power/Other
H26
VSS
Power/Other
H27
VSS
Power/Other
Table 24.Numerical Land Assignment
Land
#
Land Name
Signal Buffer
Type
Direction



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