IR3513Z

Page 17

May 11, 2009

VREF Control

The MARGIN input comparators monitor the MARGIN pin and control the internal reference voltage whose output is

sent to the VREF buffer amplifier. The output of the buffer amplifier is the VREF pin. The VREF voltage, input offsets of

error amplifier and remote sense differential amplifier are post-package trimmed to provide 0.8% system set-point

accuracy. The actual VREF voltage does not determine the system accuracy, which has a wider tolerance.

The IR3513Z can accept changes in the MARGIN input while operating and vary the VREF voltage accordingly. The

slew rate of the voltage at the VREF pin can be adjusted by an external capacitor between VREF pin and LGND pin. A

resistor connected in series with this capacitor is required to compensate the VREF buffer amplifier. Margin transitions

result in a smooth analog transition of the VREF voltage and converter output voltage minimizing inrush currents in the

input and output capacitors and overshoot of the output voltage.

Remote Voltage Sensing

VOSEN+ and VOSEN- are used for remote sensing and are connected directly to the load. The remote sense

differential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and

fast transient response.

Start-up Sequence

The IR3513Z has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor

connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay and hiccup

mode timing. A charge current of 52.5uA (typical) and discharge current of 4.5uA (typical) control the up and down slope

of the voltage at the SS/DEL pin respectively.

Figure 8 shows normal converter start-up. If there is no fault, the SS/DEL pin will start charging. The error amplifier

output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the converter’s output

voltage to match the SS/DEL voltage, less the 1.4V offset, until the converter output reaches the level determined by the

VREF (0.8 V typically) inputs. The SS/DEL voltage continues to increase until it rises above 3.12V and allows the PG

signal to be asserted. SS/DEL finally settles at 3.2V indicating the end of the soft start.

VCCL under voltage lock out, over current, as well as a low signal on the ENABLE input immediately sets the fault latch,

which causes the EAOUT pin to drive low turning off the phase IC drivers. The PG pin also drives low, and SS/DEL

begins to discharge until the voltage reaches 0.2V. If the fault has cleared the fault latch will be reset by the discharge

comparator allowing a normal soft start to occur.

Other fault conditions, such as over voltage, open sense lines, and open daisy chain, set different fault latches, which

start discharging SS/DEL, pull down EAOUT voltage and drive PG low. However, the latches can only be reset by

cycling VCCL power.

If SS/DEL pin is pulled below 0.7V, the converter can be disabled.