IR3513Z

Page 13

May 11, 2009

Phase IC1

PWM Latch SET

Control IC CLKOUT

(Phase IC CLKIN)

Control IC PHSOUT

(Phase IC1 PHSIN)

Phase IC 1 PHSOUT

(Phase IC2 PHSIN)

Phase IC 2 PHSOUT

(Phase IC3 PHSIN)

Phase IC 3 PHSOUT

(Phase IC4 PHSIN)

Phase IC4 PHSOUT

(Control IC PHSIN)

Figure 4 - Five Phase Oscillator Waveforms

PWM Operation

Upon receiving the falling edge of a clock pulse, the PWM latch is set; the PWM ramp voltage begins to increase; the

low side driver is turned off, and the high side driver is then turned on after the non-overlap time. When the PWM ramp

voltage exceeds the error amplifier’s output voltage the PWM latch is reset. This turns off the high side driver and then

turns on the low side driver after the non-overlap time and activates the ramp discharge clamp. The ramp discharge

clamp quickly discharges the PWM ramp capacitor to the output voltage of the share adjust amplifier in the phase IC

The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step

increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input

range of the PWM comparator results in up to 100% duty cycle regardless of the voltage of the PWM ramp. This

arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It

also favors response to a load step decrease, which is appropriate given the low output to input voltage ratio of most

systems. The inductor current will increase much more rapidly than decrease in response to load transients. An

additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on

operation since the PWM ramps are referenced to VREF.

Figure 5 depicts PWM operating waveforms under various conditions.