IR3513Z

Page 12

May 11, 2009

SYSTEM THEORY OF OPERATION

PWM Control Method

The PWM block diagram of the XPhase

trailing edge modulation is used. A voltage-type error amplifier with high-gain (110dB) and wide-bandwidth is used for

the control loop. It is not unity gain stable. The power-stage input voltage is sensed by the IR3513Z, and optional phase

ICs, to provide feed-forward control. The PWM ramp slope will change with the input voltage and automatically

compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output

voltage or due to the wire and PCB-trace voltage drop related to changes in load current.

VOSNS+

VOSNS-

Control Bus to

additional Phases

Power Bus to

additional Phases

IC BIAS

PWM

COMPARATOR

PWM

COMPARATOR

-

+

+

+

RAMP

DISCHARGE

CLAMP

ENABLE

BODY

BRAKING

COMPARATOR

PWM

LATCH

CURRENT

SENSE

AMPLIFIER

R

S

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

PHASE IC

REMOTE SENSE

AMPLIFIER

CCS RCS

CFB

+

-

RCS

CBST

CCS

CBST

CCOMP

RFB1

RFB

3K

CLK

D

Q

+

-

RCOMP

3K

CCOMP1

CLK

D

Q

+

-

VO

GND

VOUT

REMOTE SENSE -

REMOTE SENSE +

VCC

GATEH

CSIN-

CSIN+

GATEL

VCCL

VCCH

SW

VIN

FB

PGND

ISHARE

PHSIN

DACIN

VCC

CLKIN

VCCH

CSIN-

CSIN+

GATEL

EAIN

GATEH

PHSOUT

SW

PGND

VCCL

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

VID6

+

-

+

+

RAMP

DISCHARGE

CLAMP

ENABLE

VREF

BODY

BRAKING

COMPARATOR

CLOCK GENERATOR

DOMINANT

PWM

LATCH

CURRENT

SENSE

AMPLIFIER

ERROR

AMPLIFIER

R

S

SHARE ADJUST

ERROR AMPLIFIER

RESET

IR3513 CONTROL IC

COUT

Figure 3 - PWM Block Diagram

Frequency and Phase Timing Control

The oscillator system clock frequency is programmable from 500 kHz to 9 MHZ by an external resistor. The IR3513Z

system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is

controlled by the daisy chain loop, where the IR3513Z phase clock output (PHSOUT) is connected to the phase clock

input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC,

the IR3513Z sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to

determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows the phase timing for a four-

phase converter. For single-phase operation, PHSOUT (pin 26) and PHSIN (pin 27) must be shorted together to

prevent an Open Control Loop fault from occurring.