IR3513Z

Page 32

May 11, 2009

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

• Dedicate at least one middle layer for a ground plane.

• Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce

the noise coupling.

• Connect PGND to LGND pins to the ground plane through vias

current sense wires, but separate the two wires by ground polygon. The wire from the inductor terminal to

CSIN- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs and bootstrap

nodes.

• Place the IC, gate drive side as close as possible to the MOSFETs to reduce the parasitic resistance and

inductance of the gate drive paths.

• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET.

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