IR3513Z datasheet(2/36 Pages) IRF

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IR3513Z

Page 2

May 11, 2009

ORDERING INFORMATION

•

Samples only

PIN DESCRIPTION

Device

Package

Order Quantity

IR3513ZMTRPBF

32 Lead MLPQ (5 x 5 mm body)

3000 per reel

* IR3513ZMPBF

32 Lead MLPQ(5 x 5 mm body)

100 piece strips

PIN#

PIN SYMBOL

PIN DESCRIPTION

GATEH

High-side driver output and input to GATEL non-overlap comparator.

BOOST

Supply for high-side driver. An internal bootstrap synchronous PFET is connected

between this pin and the VCCP pin.

VCCP

Supply for low-side driver. An internal bootstrap synchronous PFET is connected

from this pin to the BOOST pin.

GATEL

Low-side driver output and input to GATEH non-overlap comparator.

PGND

Return for low side driver and reference for GATEH non-overlap comparator.

6, 24

LGND

Local Ground for internal circuitry and the IC substrate connection.

CSIN+

Non-Inverting input to the current sense amplifier and input to debug comparator.

CSIN-

Inverting input to the current sense amplifier and input to synchronous rectification

disable comparator.

ENABLE

Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float

this pin as the logic state will be undefined.

Open drain output that drives low during startup and under any external fault

condition. Connect external pull-up.

MARGIN

Tri-state input with internal pull-up to 1.425 V. Low/High voltage shifts the Error

Amplifier reference voltage Up/Down 5%. V(MARGIN) should not be biased to a

voltage greater than V(VCCL).

VOSEN-

Inverting remote sense amplifier input. Connect to ground at the load.

VOSEN+

Non-inverting remote sense amplifier input. Connect to output at the load.

14, 28

VCCL

Output of the voltage regulator, power input for clock oscillator circuitry and other

internal circuitry. Connect a decoupling capacitor to LGND.

VOUT

Remote sense amplifier output.

OVSNS

Over voltage sense input during normal operation.

Inverting input to the Error Amplifier.

EAOUT

Output of the Error Amplifier.

IIN

Average current input signal from active and inactive phase IC(s). This pin is also

used to communicate an over voltage condition to the phase IC(s).

OCSET

An external resistor tied to VREF along with a fixed internal current source

programs the constant output current limit and hiccup over-current thresholds.

Over-current protection can be disabled by programming the threshold higher than

the possible signal on the IIN pin, but no greater than 5V (do not float this pin).

VREF

Reference voltage for the Error Amplifier. An external RC network to LGND

programs the margin slew rate and compensates the internal buffer amp.

SS/DEL

An external capacitor to LGND programs converter startup and over current

protection delay timing. It is also used to compensate the constant output current

loop during soft start.

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