IR3513Z

Page 16

May 11, 2009

IR3513Z THEORY OF OPERATION

Block Diagram

The IR3513Z Block diagram is shown in Figure 7, and specific features are discussed in the following sections.

OV

UNDER

VOLTAGE

MONITOR

400K

HEADROOM

CONTROL

0V@START

EN

EN

DISABLE

VCCL UVLO

OC after VRRDY

OC before VRRDY

DETECTION PULSE

VCCL UVLO

OPEN DAISY CHAIN

VCC

VCC UVLO

OPEN SENSE LINE

IIN

HEADROOM CONTR

RESET

FAULT LATCH1

OV

OPEN SENSE LINE

VCCL UVLO

OPEN DAISY CHAIN

EAOUT

RESET

VCCL UVLO

VCCL

S

R

Q

+

-

+

-

+

-

2.2V

VCCL-0.5V

50K

50K

OV

S

R

Q

+

-

50K

+

-

+

-

S

R

Q

50K

PG

SS/DEL

MARGIN

VCCLDRV

VCCLFB

CLKOUT

VCC

ENABLE

FB

EAOUT

VREF

VOSEN-

VOSEN+

VCCL

VOUT

OVSNS

IIN

OCSET

VCCL

VCCL

VCCL

S

R

Q

RESET

DOM

GATEL ENABLE

LATCH

VID4

PHSOUT

IROSC

OC

IROSC

OC

DISABLE

IVOSEN-

VIDSEL

HR

RESET

VDACFAST

IROSC

VID0

VID0

ODC

HR

DELAY

COMPARATOR

3.2V

MARGIN INPUT

COMPARATORS

4.5uA

ENABLE

COMPARATOR

ERROR

AMPLIFIER

0.575V

850mV

800mV

VREF BUFFER

AMPLIFIER

INTERNAL

VREF

-200mV

-100mV

100% DC LIMIT

OSCILLATOR (4 PHASE APPLICATION WAVEFORM SHOWN)

250nS

BLANKING

VCC

VCCL OUTPUT

COMPARATOR

VCCL REGULATOR

AMPLIFIER

1.19V

IDCHG

RESET

DOMINANT

VR READY

LATCH

REMOTE SENSE

AMPLIFIER

0.94

0.86

0.2V

DISCHARGE

COMPARATOR

80mV

120mV

OC DELAY

COUNTER

IVOSEN+

200mV

0.4V

VCCL*0.9

IVOSEN-

SOFT

START

CLAMP

IOCSET

OC LIMIT

COMPARATOR

1.4V

OV

COMPARATOR

85mV

5mV

4 OPEN SENSE

LINE DETECT

COMPARATORS

60mV

UVLO

COMPARATOR

7.4V

7.0V

2.95V

HEADROOM CONTROL

AMPLIFIER

OC LIMIT

AMPLIFIER

+

-

UV CLEARED

FAULT LATCH2

SET

DOMINANT

SS CLEARED

FAULT LATCH1

+

-

DETECTION

PULSE

SET

DOMINANT

S

R

Q

ISOURCE

ISINK

300mV

+

-

8-Pulse

Delay

CLK

D

Q

Q

3K

INTERNAL

CIRCUIT

BIAS

S

R

Q

+

-

CLK

D

Q

OPEN CONTROL

LOOP

COMPARATOR

BOOST

LGND

GATEH

CSIN+

VCCP

CSIN-

GATEL

PGND

RMPOUT

PHSIN

PHSOUT

SW

PWM RESET

VCC

CALIBRATION

CALIBRATION

CALIBRATION

IROSC

DEBUG OFF

PHSIN

VCCL

IROSC

CURRENT SENSE

AMPLIFIER

BODY BRAKING

COMPARATOR

PWM

COMPARATOR

PWM LATCH

SHARE

ADJUST

AMPLIFIER

-

1V

X33

1V

SYNCHRONOUS

RECTIFICATION

DISABLE

COMPARATOR

+

+

+

PWM RAMP

GENERATOR

OVP

COMPARATOR

GATEL NON-

OVERLAP

COMPARATOR

GATEL

DRIVER

GATEH

DRIVER

GATEL NON-

OVERLAP LATCH

GATEH NON-

OVERLAP LATCH

SET

DOMINANT

(LOW=OPEN)

RESET

DOMINANT

X

0.75

DEBUG

COMPARATOR

SET

DOMINANT

150mV

GATEH NON-

OVERLAP

COMPARATOR

NEGATIVE CURRENT

COMPARATOR

0.8V

DACIN-SHARE_ADJ

EAIN

VID4

IOCSET-

IROSC

1.425V

4K

0.8V

+

-

VREF=0.84V

CSIN-

+

-

+

-

VREF=0.76V

ROSC/OVP

0.6V

ROSC BUFFER

AMPLIFIER

CURRENT

SOURCE

GENERATOR

OPEN CONTROL LOOP

0.897X

0V

INV

Figure 7 - Block Diagram