XMEGAA datasheet(88/445 Pages) ATMEL

88 / 445 page

8077H–AVR–12/09

XMEGA A

7.10.2

STATUS - Oscillator Status Register

• Bit 7:5 - Reserved

These bits are reserved and will always be read as zero. For compatibility with future devices,

always write these bits to zero when this register is written.

• Bit 4 - PLLRDY: PLL Ready

The PLLRDY flag is set when the PLL has locked on selected frequency and ready to be used

as he System Clock source.

• Bit 3 - XOSCRDY: External clock source Ready

The XOSCRDY flag is set when the external clock source is stable and ready to be used as the

System Clock source.

• Bit 2 - RC32KRDY: 32.768 kHz Internal RC Oscillator Ready

The RC32KRDY flag is set when the 32.768 kHz internal RC oscillator is stable and ready to be

used as the System Clock source.

• Bit 1 - RC32MRDY: 32 MHz Internal RC Oscillator Ready

The R32MRFY flag is set when the 32 MHz internal RC oscillator is stable and ready to be used

as the System Clock source.

• Bit 0 - RC2MRDY: 2 MHz Internal RC Oscillator Ready

The RC2MRDY flag is set when the 2 MHz internal RC oscillator is stable and is ready to be

used as the System Clock source.

7.10.3

XOSCCTRL - XOSC Control Register

• Bit 7:6 - FRQRANGE[1:0]: Crystal Oscillator Frequency Range Select

These bits select the frequency range for the connected crystal oscillator according to Table 7-5

on page 89.

Bit

765

+0x01

PLLRDY

XOSCRDY

RC32KRDY

R32MRDY

RC2MRDY

STATUS

Read/Write

Initial Value

Bit

+0x02

FRQRANGE[1:0]

X32KLPM

XOSCSEL[3:0]

XOSCCTRL

Read/Write

R/W

Initial Value

XMEGAA Datasheet(PDF) 88 Page - ATMEL Corporation

XMEGAA Datasheet(HTML) 88 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL