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XMEGAA Datasheet(PDF) 4 Page - ATMEL Corporation |
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XMEGAA Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 445 page  4 8077H–AVR–12/09 XMEGA A 2.1 Block Diagram Figure 2-1. XMEGA A Block Diagram Power Supervision POR/BOD & RESET PORT A (8) PORT B (8) EVENT ROUTING NETWORK EVENT ROUTING NETWORK DMA Controller BUS Controller SRAM EBI ADCA DACA ACA DACB ADCB ACB OCD PORT K (8) PORT J (8) PORT H (8) PDI CPU PH[0..7] PJ[0..7] PK[0..7] PA[0..7] PB[0..7]/ JTAG Watchdog Timer Watchdog Oscillator Interrupt Controller DATA BUS DATA BUS Prog/Debug Controller VCC GND XTAL1 XTAL2 PR[0..1] TOSC1 TOSC2 PQ[0..7] Oscillator Circuits/ Clock Generation Oscillator Control Real Time Counter Event System Controller JTAG PDI_D RESET/ PDI_CLK PORT B Sleep Controller Flash EEPROM NVM Controller DES AES IRCOM PC[0..7] PD[0..7] PE[0..7] PF[0..7] PORT G (8) PG[0..7] PORT L (8) PL[0..7] PORT M (8) PL[0..7] PP[0..7] PN[0..7] Int. Ref. AREFA AREFB Tempref VCC/10 |
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