XMEGAA datasheet(49/445 Pages) ATMEL

49 / 445 page

8077H–AVR–12/09

XMEGA A

DMA - Direct Memory Access Controller

5.1

Features

• The DMA Controller allows high-speed transfers with minimal CPU intervention

– from one memory area to another

– from memory area to peripheral

– from peripheral to memory area

– from peripheral to another peripheral

• Four DMA Channels with separate

– transfer triggers

– interrupt vectors

– addressing modes

• From 1 byte to 16M bytes data transfer in a single transaction

• Up to 64 KByte block transfers with repeat

• 1, 2, 4, or 8 byte burst transfers

• Internal and external transfer triggers

• Multiple addressing modes

– Static

–Increment

– Decrement

• Optional reload of source and destination address at the end of each

–Burst

–Block

– Transaction

• Optional Interrupt on end of transaction

• Programmable channel priority

5.2

Overview

The XMEGA Direct Memory Access (DMA) Controller is a highly flexible DMA Controller capable

of transferring data between memories and peripherals with minimal CPU intervention. The

DMA controller has flexible channel priority selection, several addressing modes, double buffer-

ing capabilities and large block sizes.

The DMA Controller can move data between memories and peripherals, between memories and

between peripheral registers directly.

There are four DMA channels that have individual source, destination, triggers and block sizes.

The different channels also have individual control settings and individual interrupt settings and

interrupt vectors. Interrupt requests may be generated both when a transaction is complete or if

the DMA Controller detects an error on a DMA channel. When a DMA channel requests a data

transfer, the bus arbiter will wait until the AVR CPU is not using the data bus and permit the DMA

Controller to transfer data. Transfers are done in bursts of 1, 2, 4 or 8 bytes. Addressing can be

static, incremental or decremental. Automatic reload of source and/or destination address can

be done after each burst transfer, block transfer, when transmission is complete, or disabled.

Both application software, peripherals and Events can trigger DMA transfers.

XMEGAA Datasheet(PDF) 49 Page - ATMEL Corporation

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