XMEGAA datasheet(28/445 Pages) ATMEL

28 / 445 page

8077H–AVR–12/09

XMEGA A

4.15.10

INTCTRL - Non-Volatile Memory Interrupt Control Register

• Bit 7:4 - Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always

write these bits to zero when this register is written.

• Bit 3:2 - SPMLVL[1:0]: SPM Ready Interrupt Level

These bits enable the Interrupt and select the interrupt level as described in ”Interrupts and Pro-

grammable Multi-level Interrupt Controller” on page 123. The interrupt is a level interrupt, which

will be triggered when the BUSY flag in the STATUS is set to logical 0. Since the interrupt is a

level interrupt note the following.

The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont

be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the

interrupt should be disabled in the interrupt handler.

• Bit 1:0 - EELVL[1:0]: EEPROM Ready Interrupt Level

These bits enable the EEPROM Ready Interrupt and select the interrupt level as described in

”Interrupts and Programmable Multi-level Interrupt Controller” on page 123. The interrupt is a

level interrupt, which will be triggered when the BUSY flag in the STATUS is set to logical 0.

Since the interrupt is a level interrupt note the following.

The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont

be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the

interrupt should be disabled in the interrupt handler.

4.15.11

STATUS - Non-Volatile Memory Status Register

• Bit 7 - NVMBUSY: Non-Volatile Memory Busy

The NVMBSY flag indicates whether the NVM memory (FLASH, EEPROM, Lock-bits) is busy

being programmed. Once a program operation is started, this flag will be set and it remains set

until the program operation is completed. he NVMBSY flag will automatically be cleared when

the operation is finished.

• Bit 6 - FBUSY: Flash Section Busy

The FBUSY flag indicate whether a Flash operation (Page Erase or Page Write) is initiated.

Once a operation is started the FBUSY flag is set, and the Application Section cannot be

accessed. The FBUSY bit will automatically be cleared when the operation is finished.

Bit

+0x0D

SPMLVL[1:0]

EELVL[1:0]

INTCTRL

Read/Write

R/W

Initial Value

Bit

5432

+0x04

BUSY

FBUSY

----

EELOAD

FLOAD

STATUS

Read/Write

RRRR

Initial Value

0000

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