MPC5606S datasheet(108/136 Pages) FREESCALE

108 / 136 page

MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

108

Figure 31. TFT LCD interface timing overview1

3.20.3.1

Interface to TFT LCD panels—pixel level timings

Figure 32 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters

shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal

(meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC

and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL

Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU

Clock Confide Register (DCCR) in the system clock module.

The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H

parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the

VSYN_PARA register.

1. In Figure 31, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and

DCU_B[0:7].

Table 57. LCD interface timing parameters—horizontal and vertical

Symbol

Parameter

Value

Unit

tPCP

D Display pixel clock period

—

tPWH

D HSYNC pulse width

PW_H

 t

PCP

tBPH

D HSYNC back porch width

BP_H

 t

PCP

tFPH

D HSYNC front porch width

FP_H

 t

PCP

tSW

D Screen width

DELTA_X

 t

PCP

tHSP

D HSYNC (line) period

(PW_H + BP_H + FP_H + DELTA_X )

 t

PCP

tPWV

D VSYNC pulse width

PWV

t

HSP

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1

LINE n

DCU_VSYNC

DCU_HSYNC

DCU_DE

DCU_CLK

DCU_LD[23:0]

m-1

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