AD9146 datasheet(5/52 Pages) AD

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AD9146

Rev. 0 | Page 5 of 52

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CMOS INPUT LOGIC LEVEL

Input VIN Logic High

1.2

Input VIN Logic Low

0.6

CMOS OUTPUT LOGIC LEVEL

Output VOUT Logic High

1.4

Output VOUT Logic Low

0.4

LVDS RECEIVER INPUTS1

Applies to data, DCI, and FRAME inputs

Input Voltage Range, VIA or VIB

825

1575

Input Differential Threshold, VIDTH

−100

+100

Input Differential Hysteresis, VIDTHH to VIDTHL

Receiver Differential Input Impedance, RIN

120

LVDS Input Rate

See Table 5

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage

Self-biased input, ac-coupled

1.25

Maximum Clock Rate

1200

MHz

REFCLK INPUT (REFCLKP, REFCLKN)

Differential Peak-to-Peak Voltage

100

500

2000

Common-Mode Voltage

1.25

REFCLK Frequency

PLL Mode

1 GHz ≤ fVCO ≤ 2.1 GHz

15.625

525

MHz

SYNC Mode

See the Multichip Synchronization

section for conditions

525

MHz

SERIAL PORT INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High (tPWH)

12.5

Minimum Pulse Width Low (tPWL)

12.5

Setup Time, SDIO to SCLK (tDS)

2.09

Hold Time, SDIO to SCLK (tDH)

0.844

Data Valid, SDIO to SCLK (tDV)

2.904

Setup Time, CS to SCLK (tDCSB)

2.38

1 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted.

DIGITAL INPUT DATA TIMING SPECIFICATIONS

Table 3.

Parameter

Value

Unit

LATENCY (DACCLK CYCLES)

1× Interpolation (With or Without Modulation)

Cycles

2× Interpolation (With or Without Modulation)

135

Cycles

4× Interpolation (With or Without Modulation)

292

Cycles

Inverse Sinc

Cycles

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