AD9146 datasheet(20/52 Pages) AD

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AD9146

Rev. 0 | Page 20 of 52

Name

Address

(Hex)

Bits

Name

Description

Default

Data Format

0x03

Binary data format

0 = input data is in twos complement format.

1 = input data is in binary format.

Q data first

Indicates I/Q data pairing on data input.

0 = I data sent to data receiver first.

1 = Q data sent to data receiver first.

MSB swap

Swaps the bit order of the data input port.

0 = order of the data bits corresponds to the pin descriptions.

1 = bit designations are swapped; most significant bits

become the least significant bits.

[1:0]

Data Bus Width[1:0]

Data receiver interface mode. See the LVDS Input Data Ports

section for information about the operation of the different

interface modes.

00 = byte mode; 8-bit interface bus width.

01 = byte mode; 8-bit interface bus width.

10 = nibble mode; 4-bit interface bus width.

11 = invalid.

Interrupt

Enable

0x04

Enable PLL lock lost

1 = enable interrupt for PLL lock lost.

Enable PLL locked

1 = enable interrupt for PLL locked.

Enable sync signal lost

1 = enable interrupt for sync signal lost.

Enable sync signal locked

1 = enable interrupt for sync signal locked.

Enable FIFO Warning 1

1 = enable interrupt for FIFO Warning 1.

Enable FIFO Warning 2

1 = enable interrupt for FIFO Warning 2.

0x05

[7:5]

Set to 0

Set these bits to 0.

000

Enable AED compare pass

1 = enable interrupt for AED comparison pass.

Enable AED compare fail

1 = enable interrupt for AED comparison fail.

Enable SED compare fail

1 = enable interrupt for SED comparison fail.

[1:0]

Set to 0

Set these bits to 0.

Event Flag

0x06

PLL lock lost

1 = indicates that the PLL, which had been previously

locked, has unlocked from the reference signal. This is a

latched signal.

N/A

PLL locked

1 = indicates that the PLL has locked to the reference

clock input.

N/A

Sync signal lost

1 = indicates that the sync logic, which had been previously

locked, has lost alignment. This is a latched signal.

N/A

Sync signal locked

1 = indicates that the sync logic has achieved sync

alignment. This is indicated when no phase changes

were requested for at least a few full averaging cycles.

N/A

FIFO Warning 1

1 = indicates that the difference between the FIFO read

and write pointers is 1.

N/A

FIFO Warning 2

1 = indicates that the difference between the FIFO read

and write pointers is 2.

N/A

Note that all event flags are cleared by writing the respective bit high.

0x07

AED compare pass

1 = indicates that the SED logic detected a valid input data

pattern compared against the preprogrammed expected

values. This is a latched signal.

N/A

AED compare fail

1 = indicates that the SED logic detected an invalid input data

pattern compared against the preprogrammed expected

values. This latched signal is automatically cleared when

eight valid I/Q data pairs are received.

N/A

SED compare fail

1 = indicates that the SED logic detected an invalid input

data pattern compared against the preprogrammed

expected values. This is a latched signal.

N/A

Note that all event flags are cleared by writing the respective bit high.

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