AD9146 datasheet(49/52 Pages) AD

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AD9146

Rev. 0 | Page 49 of 52

INTERFACE TIMING VALIDATION

The AD9146 provides on-chip sample error detection (SED)

circuitry that simplifies verification of the input data interface.

The SED circuitry compares the input data samples captured at

the digital input pins with a set of comparison values. The

comparison values are loaded into registers through the SPI

port. Differences between the captured values and the compar-

ison values are detected and stored. Options are available for

customizing SED test sequencing and error handling.

SED OPERATION

The SED circuitry operates on a data set made up of four 16-bit

input words divided into eight 8-bit input words, denoted as I0,

Q0, I1, and Q1. To properly align the input samples, the first I

data-word (that is, I0) is indicated by asserting FRAME for at

least one complete input sample.

Figure 69 shows the input timing of the interface in byte mode.

The FRAME signal can be issued once at the start of the data

transmission, or it can be asserted repeatedly at intervals coinciding

with the I0 and Q0 data-words.

FRAME

DATA

I0MSB

I0LSB

Q0MSB

Q0LSB

I1MSB

I1LSB

Q1MSB

Q1LSB

Figure 69. Timing Diagram of Extended FRAME Signal Required to Align

Input Data for SED

The SED has three flag bits (Register 0x67, Bit 5, Bit 1, and

Bit 0) that indicate the results of the input sample comparisons.

The sample error detected bit (Register 0x67, Bit 5) is set when

an error is detected and remains set until cleared. The SED also

provides registers that indicate which input data bits experienced

errors (Register 0x70 through Register 0x73). These bits are latched

and indicate the accumulated errors detected until cleared.

Autosample error detection (AED) is an autoclear function in the

SED. The autoclear mode has two effects: it activates the compare

fail bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and

changes the behavior of Register 0x70 through Register 0x73. The

compare pass bit is set if the last comparison indicated that the

sample was error free. The compare fail bit is set if an error is

detected. The compare fail bit is automatically cleared by the

reception of eight consecutive error-free comparisons. When

autoclear mode is enabled, Register 0x70 through Register 0x73

accumulate errors as previously described but are reset to all 0s

after eight consecutive error-free sample comparisons are made.

If desired, the sample error detected, compare pass, and compare

fail flags can be configured to trigger the IRQ pin when active.

This is done by enabling the appropriate bits in the event flag

Table 26 shows a progression of the input sample comparison

results and the corresponding states of the error flags.

Table 26. Progression of Input Sample Comparison Results and the Resulting SED Register Values

Compare Results (Pass/Fail)

(Errors detected bits)

1 Z = all 0s.

2 N = nonzero.

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