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TUSB1310A Datasheet(PDF) 34 Page - Texas Instruments |
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TUSB1310A Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 42 page ![]() VDD1P1 VDD1P8 and Analog Power Supplies OUT_ENABLE XI RESETN Latch-In of Hardware Strapping Pins ULPI_DIR Tcfgin1 Drive Output Strapping pins Tcfgin2 TUSB1310A SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011 www.ti.com Figure 6-1. Power Up and Reset Timing Table 6-1. Power Up and Reset Timing DESCRIPTION SYMBOL MIN TYP MAX UNITS Hardware configuration latch-in time from RESETN Tcfgin1 0 ns Time from RESETN to driver outputs on strapping pins Tcfgin2 0 ns RESETN pulse width 1 µs RESETN to PHY_STATUS de-assertion 300 µs 6.5.2 PIPE Transmit Figure 6-2. PIPE Transmit Timing Table 6-2. PIPE Transmit Timing DESCRIPTION SYMBOL MIN TYP MAX UNITS TX_CLK period Tcyc2 4 ns TX_CLK duty cycle Tdty2 50 % Data setup to TX_CLK rise and TX_CLK fall(1) Tsu2 1 ns Data hold to TX_CLK rise and TX_CLK fall(1) Thd2 0 ns (1) This includes TX_DATA15-0, TX_DATAK1-0, TX_ONESZEROS, RATE, TX_DEEMPTH, TX_DETRX_LPBK, TX_ELECIDLE, TX_MARGIN, TX_SWING, RX_POLARITY, POWER_DOWN1-0. 34 ELECTRICAL SPECIFICATIONS Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310A |
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