TUSB1310A datasheet(35/42 Pages) TI

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PCLK

RX_DATA15-0

RX_DATAK1-0

RX_VALID

RX_STATUS2-0

PHY_STATUS

Valid Data

Tcyc3

Tdly3

TUSB1310A

www.ti.com

SLLSE32D

– NOVEMBER 2010 – REVISED MAY 2011

6.5.3

PIPE Receive

Figure 6-3. PIPE Receive Timing

Table 6-3. PIPE Receive Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Tcyc3

PCLK Period

Tdty3

PCLK Duty Cycle

PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID,

Tdly3

RX_STATUS2-0, PHY_STATUS Delay(1)(2)

(1)

Output Load max = 10 pF, min = 5 pF

(2)

Timing is relative to the 50% transition point, not VIH/VIL.

6.5.4

ULPI Parameters

Table 6-4. ULPI Parameters

DESCRIPTION

NOTES

UNIT

RX CMD delay

2-4

clocks

TX start delay

1-2

1-10

clocks

TX end delay

PHY pipeline delays

2-5

clocks

RX start delay

3-8

clocks

RX end delay

3-8

17-18

122-123

clocks

Transmit-Transmit (host only)

15-24

7-18

77-247

clocks

Link decision times

Receive-Transmit (host or peripheral)

1-14

7-18

77-247

clocks

6.5.5

ULPI Clock

Table 6-5. ULPI Clock Parameters

DESCRIPTION

SYMBOL

MIN

TYP

MAX

UNITS

Frequency (first transition)

±10%

Fstart_8bit

MHz

Frequency (steady state)

±500 ppm

Fsteady

59.97

60.03

MHz

Duty cycle (first transition)

±10%

Dstart_8bit

Duty cycle (steady state)

±500 ppm

Dsteady

49.97 5

50.02 5

Time to reach steady state frequency and duty cycle after

Tsteady

1.4

first transition

Clock startup time after deassertion of SuspemdM

–

Tstart_dev

5.6

Peripheral

Clock startup time after deassertion of SuspemdM

– Hold

Tstart_host

PHY preparation time after first transition of input clock

Tprep

µs

Jitter

Tjitter

ELECTRICAL SPECIFICATIONS

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