MCP3903 datasheet(28/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 28

5.7

Power-on Reset

The MCP3903 contains an internal POR circuit that

monitors analog supply voltage AVDD during operation.

The typical threshold for a power-up event detection is

4.2V ±5%. The POR circuit has a built-in hysteresis for

improved transient spikes immunity that has a typical

value of 200 mV. Proper decoupling capacitors (0.1 µF

ceramic and 10 µF tantalum) should be mounted as

close as possible to the AVDD pin, providing additional

transient immunity.

Figure 5-3 illustrates the different conditions at

power-up and a power-down event, in typical

conditions. All internal DC biases are not settled until at

least 50 µs after system POR. Any data ready pulses

during this time after system reset should be ignored.

After POR, data ready pulses are present at the pin

with all the default conditions in the configuration regis-

ters.

Both AVDD and DVDD power supplies are independent.

Since AVDD is the only power supply that is monitored,

it is highly recommended to power up DVDD first as a

power-up sequence. If AVDD is powered up first, it is

highly recommended to keep the RESET pin low during

the whole power-up sequence.

FIGURE 5-3:

Power-on Reset Operation.

5.8

RESET Effect On Delta Sigma

Modulator/SINC Filter

When the RESET pin is low, both ADCs will be in Reset

and output code 0x0000h. The RESET pin performs a

hard reset (DC biases still on, part ready to convert)

and clears all charges contained in the sigma delta

modulators. The comparator outputs are 0011 for each

ADC.

The SINC filters are all reset, as well as their double

output buffers. This pin is independent of the serial

interface. It brings the CONFIG registers to the default

state. When RESET is low, any write with the SPI

interface will be disabled and will have no effect. All

output pins (SDO, DR, MDAT0/1) are high impedance,

and no clock is propagated through the chip.

5.9

Phase Delay Block

The MCP3903 incorporates a phase delay generator

which ensures that the six ADCs are converting the

inputs with a fixed delay between them. The six ADCs

are synchronously sampling but the averaging of

modulator outputs is delayed so that the SINC filter

outputs (thus the ADC outputs) show a fixed phase

delay, as determined by the PHASE register setting.

The phase register is composed of three bytes:

PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each

byte is a 7 bit + sign MSB first, two's complement code

that represents the amount of delay between each pair

of ADCs. The PHASEC byte represents the delay

between Channel 4 and channel 5 (pair C). The

PHASEB byte represents the delay between Channel 2

and channel 3 (pair B). The PHASEA byte represents

the delay between Channel 0 and channel 1 (pair A).

The reference channel is the odd channel (channel 1/

3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is

lagging versus channel 1/3/5 otherwise it is leading.

The amount of delay between two ADC conversions is

given by the following formula:

EQUATION 5-5:

The timing resolution of the phase delay is 1/DMCLK or

1 µs in the default configuration with MCLK = 4 MHz.

The data ready signals are affected by the phase delay

settings. Typically, the time difference between the data

ready pulses of channel 0 and channel 1 is equal to the

phase delay setting.

AVDD

4.2V

DEVICE

MODE

RESET

PROPER

OPERATION

RESET

Time

50 µs

tPOR

Note:

A detailed explanation of the Data Ready

pins (DRn) with phase delay is present in

Section 6.10

“Data

Ready

Pulses

(DRn)”

Delay

Phase Register Code

DMCLK

--------------------------------------------------

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