MCP3903 datasheet(42/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 42

7.5

STATUS/COM Register - Status

and Communication Register

7.5.1

DATA READY LATENCY - DR_LTY

This bit determines if the data ready pulses correspond

to settled data or unsettled data from each SINC3 filter.

Unsettled data will provide data ready pulses every

DRCLK period. Settled data will wait for 3 DRCLK

periods before giving data ready pulses and will then

give data ready pulses every DRCLK period.

7.5.2

DATA READY HIGH Z MODE -

DR_HIZ

Using this bit, the user can connect multiple chips with

the same data ready pin with a pull up resistor

(DR_HIZ=0) or a single chip with no external compo-

nent (DR_HIZ=1)

7.5.3

DATA READY MODE - DRN_MODE

These bits control which ADC data ready is present on

the data ready pin. When the bits are set to 00, the

output of the two ADCs are latched synchronously at

the moment of the data ready event. This prevents bad

synchronization between the two ADCs. The output is

also latched at the beginning of a reading, in order not

to be updated during a read, and not to give erroneous

data.

If one of the channels is in reset or shutdown, only one

of the data ready pulses is present and the situation is

similar to DRn_MODE<1:0> = 01 or 10. In the 01,10

and 11 modes, the data is latched at the beginning of a

reading, in order to prevent the case of erroneous data

when a data ready pulse happens when reading.

7.5.4

DATA READY STATUS FLAG -

DRSTATUS_CHN

These bits indicate the data ready status of each chan-

nel. These flags are set to logic high after being the

STATUS/COM register has been read. These bits are

cleared when a data ready event has happened on its

respective ADC. Writing these bits has no effect.

TABLE 7-7:

STATUS/COM Register

Name

Bits

Address

Cof

STATUS/COM

0x09

R/W

Note:

These bits are useful if multiple devices

the

same

DRn

output

(DR_HIZ=0) in order to understand which

device the data ready event occured from.

In case the DRn_MODE=00 (Linked

ADCs), these data ready status bits will be

updated synchronously upon the same

event (lagging ADC is ready). These bits

are also useful in systems where the DRn

pins are not used to save MCU I/O.

STATUS/COM REGISTER

R/W-1

R/W-0

WMODE

WIDTH_CH5

WIDTH_CH4

WIDTH_CH3

WIDTH_CH2

WIDTH_CH1

bit 23

bit 16

R/W-0

R/W-1

R/W-0

WIDTH_CH0

DR_LTY

DR_HIZ

DR_LINK

DRC_MODE1

DRC_MODE0

DRB_MODE1

DRB_MODE0

bit 15

bit 8

R/W-0

R-1

DRA_MODE1

DRA_MODE0 DRSTATUS_CH5 DRSTATUS_CH4 DRSTATUS_CH3 DRSTATUS_CH2 DRSTATUS_CH1 DRSTATUS_CH0

bit 7

bit 0

bit 23:22

READ[1:0]:

Address Loop Setting

= Address counter incremented, cycle through entire register map

= Address counter loops on register TYPES (DEFAULT)

= Address counter loops on register GROUPS

= Address not incremented, continually read single register

bit 21

WMODE:

Write Mode Bit (internal use only)

= Static addressing Write Mode

= Incremental addressing Write Mode (DEFAULT)

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