MCP3903 datasheet(29/54 Pages) MICROCHIP

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DS25048B-page 29

MCP3903

5.9.1

PHASE DELAY LIMITS

The Phase delay can only go from -OSR/2 to +OSR/2 - 1.

This sets the fine phase resolution. The phase register is

coded with 2's complement.

If larger delays between the two channels from the

same pair are needed, they can be implemented exter-

nally to the chip with an MCU. A FIFO in the MCU can

save incoming data from the leading channel for a

number N of DRCLK clocks. In this case, DRCLK

would represent the coarse timing resolution, and

DMCLK the fine timing resolution. The total delay will

then be equal to:

Delay = N/DRCLK + PHASE/DMCLK

The Phase Delay register can be programmed once

with the OSR=256 setting and will adjust to the OSR

automatically afterward without the need to change the

value of the PHASE register.

• OSR=256: the delay can go from -128 to +127.

PHASEn<7> is the sign bit. PHASEn<6> is the

MSB and PHASEn<0> the LSB.

• OSR=128: the delay can go from -64 to +63.

PHASEn<6> is the sign bit. PHASEn<5> is the

MSB and PHASEn<0> the LSB.

• OSR=64: the delay can go from -32 to +31.

PHASEn<5> is the sign bit. PHASEn<4> is the

MSB and PHASEn<0> the LSB.

• OSR=32: the delay can go from -16 to +15.

PHASEn<4> is the sign bit. PHASEn<3> is the

MSB and PHASEn<0> the LSB.

5.10

Crystal Oscillator

The MCP3903 includes a Pierce-type crystal oscillator

with very high stability and ensures very low tempco

and jitter for the clock generation. This oscillator can

handle up to 16.384 MHz crystal frequencies, provided

that proper load capacitances and quartz quality factor

are used.

For keeping specified ADC accuracy, AMCLK should

be kept between 1 and 5 MHz with BOOST off or 1 and

8.192 MHz with BOOST on. Larger MCLK frequencies

can be used, provided the prescaler clock settings

allow the AMCLK to respect these ranges.

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND and

between OSC2 and DGND. They should also respect

the following equation:

EQUATION 5-6:

When CLKEXT=1, the crystal oscillator is bypassed by

a digital buffer to allow direct clock input for an external

clock.

TABLE 5-7:

PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 256

Phase Register

Value

Hex

Delay

(CH0/2/4 relative

to CH1/3/5)

011 11111

0x7F

+ 127 µs

011 11110

0x7E

+ 126 µs

000 00001

0x01

+ 1 µs

000 00000

0x00

0 µs

111 11111

0xFF

- 1 µs

100 00001

0x81

- 127 µs

100 00000

0x80

-128 µs

1.6

CLOAD

-----------------------------

⎝⎠

⎛⎞

Where:

crystal frequency in MHz

CLOAD

load capacitance in pF including

parasitics from the PCB

motional resistance in ohms of

the quartz

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