MCP3903 datasheet(40/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 40

7.3

Phase Register

The phase register is composed of three bytes:

PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each

byte is a 7 bit + sign MSB first, two's complement code

that represents the amount of delay between each pair

of ADCs. The PHASEC byte represents the delay

between Channel 4 and Channel 5 (pair C). The

PHASEB byte represents the delay between Channel 2

and Channel 3 (pair B). The PHASEA byte represents

the delay between Channel 0 and Channel 1 (pair A).

The reference channel is the odd channel (Channel 1/

3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is

lagging versus channel 1/3/5 otherwise it is leading.

The delay is calculated by the following formula:

Delay = PHASE Register Code / DMCLK.

TABLE 7-5:

PHASE REGISTER

Name

Bits

Address

Cof

PHASE

0x07

R/W

PHASE REGISTER

R/W-0

PHASEC7

PHASEC6

PHASEC5

PHASEC4

PHASEC3

PHASEC2

PHASEC1

PHASEC0

bit 23

bit 16

R/W-0

PHASEB7

PHASEB6

PHASEB5

PHASEB4

PHASEB3

PHASEB2

PHASEB1

PHASEB0

bit 15

bit 8

R/W-0

PHASEA7

PHASEA6

PHASEA5

PHASEA4

PHASEA3

PHASEA2

PHASEA1

PHASEA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23:16

PHASECn:

CH4 relative to CH5 phase delay

bit 15:8

PHASEBn:

CH2 relative to CH3 phase delay

bit 7:0

PHASEAn:

CH0 relative to CH1 phase delay

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