MCP3903 datasheet(36/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 36

6.11

DATA READY PULSE WITH

PHASE DELAY

To ensure that both channel ADC data from the same

pair are present at the same time for SPI read, regard-

less of phase delay settings for either or both channels,

there are two sets of latches in series with both the data

ready and the reading start triggers. The first latch is set

on whichever channel is the lagging channel (relative to

the other channel, in a single channel pair). The second

latch is set when an ADC output read command is

issued, ensuring synchronized data ready pulses.

FIGURE 6-9:

Internal Latches

Synchronizing Data Ready Pulses with Phase

Delay Present (Single Channel Pair Shown).

6.11.1

DATA READY LINK

When DRLINK=0, the three pairs of ADCs are

independent from each other. The data readys and the

latches for the output data only depend on both ADCs

in the pair. When another ADC (not in the pair) is put in

SHUTDOWN or RESET, it has no effect.

When DRLINK=1, all ADCs are linked together. The

DRn_MODE<1:0> are all set internally to 00. All

DRn_MODE<1:0> bits are not taken into account.

All six channel ADC data are latched synchronously

with the most lagging ADC channel of the six.

All three DRA, DRB and DRC data ready pins are

giving the same output that is synchronized with the

most lagging ADC of the six channels. Only one pin can

be connected to the MCU in this mode, which saves

two connection ports on the MCU.

In this mode, if any channel is in SHUTDOWN or

RESET mode, no data ready is present on any of the

DRA/DRB/DRC pins. The part acts as if there was only

one ADC channel with 6x24 bits.

Depending on the read modes, the ADC data can be

retrieved by pair (Read by GROUP) or all together

(Read by TYPE). Any time a new read command is per-

formed, the ADC outputs are re-latched. In order to

avoid loss of data or bad synchronization, the read

mode by TYPES is recommended (READ<1:0>=10) so

that all data can be latched once at the beginning of the

read. In the read mode by GROUP (READ<1:0>=01)

mode, the data will be relatched every time the part

accesses to each group or pair of ADCs.

CHn ADC

LATCH

SPI Serial

Interface

CHn ADC

LATCH

Synchronized

data ready pulses

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