MCP3903 datasheet(16/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 16

3.10

Oscillator And Master Clock Input

Pins (OSC1/CLKI, OSC2)

OSC1/CLKI and OSC2 provide the master clock for the

device. When CLKEXT = 0 (Default), a resonant

crystal or clock source with a similar sinusoidal

waveform must be placed across these pins to ensure

proper operation. The typical clock frequency specified

is 4 MHz. However, the clock frequency can be 1 MHz

to 5 MHz without disturbing ADC accuracy. With the

current boost circuit enabled, the master clock can be

used up to 8.192 MHz without disturbing ADC

accuracy. Appropriate load capacitance should be

connected to these pins for proper operation.

3.11

CS (Chip Select)

This pin is the SPI Chip Select that enables the serial

communication.

When

this

high,

communication can take place. A chip select falling

edge initiates the serial communication and a chip

select rising edge terminates the communication. No

communication can take place even when CS is low

and when RESET is low.

This input is Schmitt-triggered.

3.12

SCK (Serial Data Clock)

This is the serial clock pin for SPI communication. Data

is clocked into the device on the RISING edge of SCK.

Data is clocked out of the device on the FALLING edge

of SCK. The MCP3903 interface is compatible with

both SPI 0,0 and 1,1 modes. The maximum clock

speed specified is 10 MHz. This input is Schmitt

triggered.

3.13

SDO (Serial Data Output)

This is the SPI data output pin. Data is clocked out of

the device on the FALLING edge of SCK. This pin stays

at high impedance during the control byte. It also stays

at high impedance during the whole communication for

write commands and when the CS pin is high or when

the RESET pin is low. This pin is active only when a

read command is processed. Each read is processed

by a packet of 24 bits (size of each register), except on

the ADC output registers when WIDTH=0.

3.14

SDI (Serial Data Input)

This is the SPI data input pin. Data is clocked into the

device on the RISING edge of SCK. When CS is low,

this pin is used to communicate with a series of 8-bit

commands. The interface is half-duplex (inputs and

outputs do not happen at the same time). Each

communication starts with a chip select falling edge

followed by an 8-bit control byte entered through the

SDI pin. Each write is processed by packets of 24 bits

(size of each register). Each command is either a Read

or a Write command. Toggling SDI during a Read

command has no effect. This input is Schmitt-triggered.

Note:

When CLKEXT = 1, the crystal oscillator

is disabled, as well as the OSC2 input.

The OSC1 becomes the master clock

input CLKI, direct path for an external

clock source, for example a clock source

generated by an MCU.

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