MCP3903 datasheet(33/54 Pages) MICROCHIP

33 / 54 page

DS25048B-page 33

MCP3903

6.7.1

CONTINUOUS READ

All ADCs are powered up with their default

configurations, and begin to output data ready pulses

immediately (RESET<5:0> and SHUTDOWN<5:0>

bits are off by default). The default output codes for

both ADCs are all zeros.The default modulator output

for both ADCs is 0011 (corresponding to a theoretical

zero voltage at the inputs). The default phase is zero

between the two channels. It is recommended to enter

into ADC reset mode for both ADCs just after power-up

because the desired MCP3903 register configuration

may not be the default one and in this case, the ADC

would output undesired data. Within the ADC reset

mode (RESET<5:0>=111111), the user can configure

the whole part with a single communication. The write

commands automatically increment the address so the

user can start writing the PHASE register and finish

with the CONFIG register in only one communication

(see Figure 6-6). The RESET<5:0> bits are in the

CONFIG register to allow it to exit soft reset mode and

have the whole part configured and ready to run in only

one command.

The following internal registers are defined as types:

6.8

Situations that Reset ADC Data

Immediately after the following actions, the ADCs are

reset and automatically restarted in order to provide

proper operations:

Change in phase register

Change in the OSR setting

Change in the PRESCALER setting

Overwrite of identical PHASE register

value

Change in EXTCLK bit in the CONFIG

After these temporary resets, the ADCs go back to

normal operation with no need for an additional

command. These are also the settings where the DR

position is affected. The phase register can be used to

soft reset the ADC without using the RESET bits in the

configuration register.

6.9

Line Cycle Sampling Options

Since the AMCLK range can go up to 5 MHz, the

MCP3903 is able to accommodate 256 output samples

per line cycles with line frequencies up to 76.2Hz at

OSR=64.

Figure 6-7 illustrates operating the part in this manner

(timings not to scale, functional description only).

All channels are continuously converting during normal

operation of the device except when it is in Sleep Mode

by using the RESET bit, or if RESET is low. The

following figure represents the clocking scheme and

how

the

CONFIG

PRESCALE<1:0>

bits

and

OSR<1:0> bits registers is used to modify the clock

prescale and oversampling ratio.

For example, if a data ready pulse occurs while ADC

data (a) is being transmitted on SPI, this data will not

be corrupt in any way. After CS is toggled low to begin

another transmission, the next data (b) would be

present in the output buffer ready for transmission.

TABLE 6-1:

GROUP

ADDRESSES

Pair A, CHANNEL 0/1

0x00 - 0x01

Pair B, CHANNEL 2/3

0x02 - 0x03

Pair C, CHANNEL 4/5

0x04 - 0x05

MOD, PHASE, GAIN

0x06 - 0x08

STATUS, CONFIG

0x09 - 0x0A

TABLE 6-2:

TYPE

ADDRESSES

ADC DATA

0x00 - 0x05

CONTROL

0x06 - 0x0A

TABLE 6-1:

MCLK FREQUENCIES FOR

LINE SAMPLING

OUTPUT

SAMPLES

/ LINE

CYCLE

FLINE = 45 HZ

OSR = 64

FLINE = 65 HZ

OSR = 64

MCLK

2.8 ksps

737.28 kHz

4.2 ksps

1.075 MHz

128

5.76 ksps

1.475 MHz

8.4 ksps

2.15 MHz

256

11.5 ksps

2.949 MHz

16.7 ksps

4.3 MHz

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