OPA699M datasheet(25/32 Pages) TI

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Limiter Headroom (V)

1.0

0.5

4.0

4.5

3.5

3.0

2.5

2.0

1.5

5.0

100

-25

-50

-75

-100

Maximum Over Temperature

Minimum Over Temperature

Limiter Headroom = +V

S - VH

= V

L - (-VS)

Current = I

VH or -IVL

G027

± Limit Voltage (V)

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7 1.8

1.9

2.0

-40

-50

-60

-70

-80

-90

3rd-Harmonic

2nd-Harmonic

O = 0VDC ± 1VP

f = 5MHz

L = 500Ω

G019

OPA699M

SGLS289A – MAY 2005 – REVISED MARCH 2006

Figure 58. Limit Bias Current vs Bias Voltage

When the limiter voltages are more than 2.1 V from the supplies (VL = –VS + 2.1 V or VH = +VS– 2.1 V), you can

use simple resistor dividers to set VH and VL (see Figure 47). Make sure to include the limiter input bias currents

(see Figure 54) in the calculations (that is, IVL = 50 µA into pin 5, and IVH = +50 µA out of pin 8). For good limiter

voltage accuracy, run a minimum 1-mA quiescent bias current through these resistors. When the limiter voltages

need to be within 2.1 V of the supplies (VL = –VS + 2.1 V or VH = +VS– 2.1 V), consider using low impedance

buffers to set VH and VL to minimize errors due to bias current uncertainty. This condition typically is the case for

single-supply operation (VS = +5 V). Figure 48 runs 2.5 mA through the resistive divider that sets VH and VL. This

limits errors due to IVH and IVL < ±1% of the target limit voltages. The limiters' dc accuracy depends on attention

to detail. The two dominant error sources can be improved as follows:

•

Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (for

example, ±5%). Using a more accurate source and bypassing pins 5 and 8 with good capacitors, improves

limiter PSRR.

•

The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. Other error sources also

contribute, but should have little impact on the limiters' dc accuracy.

•

Reduce offsets caused by the limiter input bias currents. Select the resistors in the resistive divider(s) as

described above.

•

Consider the signal path dc errors as contributing to uncertainty in the useable output swing.

•

The limiter offset voltage only slightly degrades limiter accuracy. Figure 59 shows how the limiters affect

distortion performance. Virtually no degradation in linearity is observed for output voltage swinging right up to

the limiter voltages. In this plot a fixed ±1-V output swing is driven while the limiter voltages are reduced

symmetrically. Until the limiters are reduced to ±1.1 V, little distortion degradation is observed.

Figure 59. Harmonic Distortion Near Limit Voltages

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