www.ti.com

R

G

R

F

R

S

OPA699

I

BI

E

O

I

BN

E

RS

E

NI

4kT

R

G

4kT = 1.6E -20J

at 290 K

4kTR

F

S0049-02

4kTR

S

E

O +

E

NI

2

) IBNRS

2

) 4kTRS NG

2

) 4kTRFNG

(7)

E

N +

E

NI

2

) IBNRS

2

) 4kTRS )

I

BI

R

F

NG

2

)

4kTR

F

NG

(8)

DC-Accurracy and Offset Control

OPA699M

SGLS289A – MAY 2005 – REVISED MARCH 2006

Figure 62. Op Amp Noise Analysis Model

The total output spot noise voltage can be computed as the square root of the sum of all squared output noise

voltage contributors. Equation 7 shows the general form for the output noise voltage using the terms shown in

Figure 62.

voltage at the noninverting input, as shown in Equation 8.

Evaluating these two equations for the OPA699 circuit and component values (see Figure 47) gives a total output

spot noise voltage of 27.4 nV/

√Hz and a total equivalent input spot noise voltage of 4.6 nV/√Hz. This total

input-referred spot noise voltage is only slightly higher than the 4.1-nV/

√Hz specification for the op amp voltage

noise alone. This is the case as long as the impedances appearing at each op amp input are limited to a

maximum value of 300

Ω. Keeping both (R

satisfies both noise and frequency response flatness considerations. Since the resistor-induced noise is

amp configuration of Figure 49 is not required, but is still desirable.

The balanced input stage of a wideband voltage feedback op amp allows good output dc accuracy in a large

variety of applications. The power-supply current trim for the OPA699 gives even tighter control than comparable

products. Although the high-speed input stage does require relatively high input bias current (typically 3 µA at

each input terminal), the close matching between them may be used to reduce the output dc error caused by this

current. The total output offset voltage may be considerably reduced by matching the dc source resistances

appearing at the two inputs. This reduces the output dc error due to the input bias currents to the offset current

times the feedback resistor. Evaluating the configuration of Figure 47, using worst-case +25°C input offset

voltage and current specifications, gives a worst-case output offset voltage, with NG = noninverting signal gain,

equal to:

= ±(2 × 8 mV) ± (750

Ω × 3 µA)

= ±18.3 mV

28

Submit Documentation Feedback