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AFE030 Datasheet(PDF) 38 Page - Texas Instruments

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Part # AFE030
Description  Powerline Communications Analog Front-End
PDF  58 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AFE030 Datasheet(HTML) 38 Page - Texas Instruments

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AFE030
SBOS588A
– DECEMBER 2011 – REVISED DECEMBER 2011
www.ti.com
Table 12. Control1 Register: Address 04h
Default: 00h
Control1 Register
<7:0>
LOCATION
BIT NAME
(0 = LSB)
DEFAULT
R/W
FUNCTION
This bit is used to enable/disable the TX calibration mode.
TX_CAL
0
0
R/W
0 = Disabled
1 = Enabled
This bit is used to enable/disable the RX calibration mode.
RX_CAL
1
0
R/W
0 = Disabled
1 = Enabled
This bit is used to enable/disable the TX PGA calibration mode.
TX_PGA_CAL
2
0
R/W
0 = Disabled
1 = Enabled
This bit is used to select the frequency response of the Tx filter and
Rx filter.
CA_CBCD
3
0
R/W
0 = CENELEC A
1 = CENELEC B, C, D
—
4
0
—
Reserved
—
5
0
—
Reserved
This bit is used to indicate the status of the Tx block.
TX_FLAG
6
0
R
0 = Tx block is not ready for transmission
1 = Tx block is ready for transmission
This bit is used to indicate the status of the Rx block.
RX_FLAG
7
0
R
0 = Rx block is not ready for reception
1 = Rx block is ready for reception
Table 13. Control2 Register: Address 05h
Default: 01h
Control2 Register
<7:0>
LOCATION
BIT NAME
(0 = LSB)
DEFAULT
R/W
FUNCTION
—
0
0
—
Reserved
—
1
0
—
Reserved
—
2
0
—
Reserved
—
3
0
—
Reserved
—
4
0
—
Reserved
This bit is used to enable/disable the T_flag bit in the RESET
Register.
T_FLAG_EN
5
0
R/W
0 = Disabled
1 = Enabled
This bit is used to enable/disable the I_flag bit in the RESET
Register.
I_FLAG_EN
6
0
R/W
0 = Disabled
1 = Enabled
—
7
X
—
Reserved
38
Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): AFE030



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