AFE030 datasheet(39/58 Pages) TI1

39 / 58 page

AFE030

www.ti.com

SBOS588A

– DECEMBER 2011 – REVISED DECEMBER 2011

Table 14. RESET Register: Address 09h

Default: 00h

Reset Register

<7:0>

LOCATION

BIT NAME

(0 = LSB)

DEFAULT

R/W

FUNCTION

Reserved

SOFTRST0,

These bits are used to perform a software reset of the ENABLE1,

SOFTRST1,

2, 3, 4

0, 0, 0

ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT

SOFTRST2

registers. Writing '101' to these registers performs a software reset.

This bit is used to indicate the status of a PA thermal overload.

0 = On read, indicates that no thermal overload has occurred since

the last reset.

T_FLAG

R/W

0 = On write, resets this bit.

1 = On read, indicates that a thermal overload has occurred since

the last reset. Remains latched until reset.

This bit is used to indicate the status of a PA output current

overload.

0 = On read indicates that no current overload has occurred since

I_FLAG

R/W

the last reset.

0 = On write, resets this bit.

1 = On read indicates that a current overload has occurred since

the last reset. Remains latched until reset.

—

Reserved

Table 15. DieID Register: Address 0Ah

Default: 01h

DieID Register

<7:0>

LOCATION

BIT NAME

(0 = LSB)

DEFAULT

R/W

FUNCTION

DIE ID

<0>

The DieID Register is hard-wired.

DIE ID

<1>

The DieID Register is hard-wired.

DIE ID

<2>

The DieID Register is hard-wired.

DIE ID

<3>

The DieID Register is hard-wired.

DIE ID

<4>

The DieID Register is hard-wired.

DIE ID

<5>

The DieID Register is hard-wired.

DIE ID

<6>

The DieID Register is hard-wired.

DIE ID

<7>

The DieID Register is hard-wired.

Table 16. Revision Register: Address 0Bh

Default: 02h

Revision Register

<7:0>

LOCATION

BIT NAME

(0 = LSB)

DEFAULT

R/W

FUNCTION

REVISION ID

<0>