AM1802 datasheet(97/180 Pages) TI1

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AM1802

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SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012

Figure 5-23 shows the routing for the DQGATE net class. Table 5-36 contains the routing specification.

Figure 5-23. DQGATE Routing

Table 5-36. DQGATE Routing Specification

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DQGATE Length F

CKB0B(1)

Center to center DQGATE to any other trace spacing

4w(2)

DQS/D nominal trace length

DQLM-50

DQLM

DQLM+50

Mils

DQGATE Skew(3)

100

Mils

(1)

CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2)

w = PCB trace width as defined in Table 5-27.

(3)

Skew from CKB0B1

5.11.3.12 MDDR/DDR2 Boundary Scan Limitations

Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells

between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are

tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects

between functional and boundary scan paths.

The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output

enable cells on the DDR pins and this is a violation of IEEE 1149.1. Full EXTEST and PRELOAD

capability is still available.

Peripheral Information and Electrical Specifications

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