AM1802 datasheet(10/180 Pages) TI1

10 / 180 page

AM1802

SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012

www.ti.com

Table 2-2. AM1802 Top Level Memory Map (continued)

Start Address

End Address

Size

ARM Mem Map

EDMA Mem Map

Master Peripheral Mem Map

0x01E2 D000

0x01E2 FFFF

0x01E3 0000

0x01E3 7FFF

32K

EDMA3 CC1

0x01E3 8000

0x01E3 83FF

EDMA3 TC2

0x01E3 8400

0x01F0 BFFF

0x01F0 C000

0x01F0 CFFF

Timer2

0x01F0 D000

0x01F0 DFFF

Timer3

0x01F0 E000

0x01F0 EFFF

SPI1

0x01F0 F000

0x3FFF FFFF

0x4000 0000

0x5FFF FFFF

512M

EMIFA SDRAM data (CS0)

0x6000 0000

0x61FF FFFF

32M

EMIFA async data (CS2)

0x6200 0000

0x63FF FFFF

32M

EMIFA async data (CS3)

0x6400 0000

0x65FF FFFF

32M

EMIFA async data (CS4)

0x6600 0000

0x67FF FFFF

32M

EMIFA async data (CS5)

0x6800 0000

0x6800 7FFF

32K

EMIFA Control Regs

0x6800 8000

0x7FFF FFFF

0x8000 0000

0x8001 FFFF

128K

On-Chip RAM

0x8002 0000

0xAFFF FFFF

0xB000 0000

0xB000 7FFF

32K

DDR2 Control Regs

0xB000 8000

0xBFFF FFFF

0xC000 0000

0xDFFF FFFF

512M

DDR2 Data

0xE000 0000

0xFFFC FFFF

0xFFFD 0000

0xFFFD FFFF

64K

ARM local ROM

0xFFFE 0000

0xFFFE DFFF

0xFFFE E000

0xFFFE FFFF

ARM Interrupt Controller

0xFFFF 0000

0xFFFF 1FFF

ARM local RAM

0xFFFF 2000

0xFFFF FFFF

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