GRAYCHIP, INC.

- 17 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

4.2

SYNC CONTROL REGISTERS

Control registers SYNC_REG0 and SYNC_REG1 determine how the circuits within the chip are

synchronized. Each circuit which requires synchronization can be configured to be synchronized to the sync

inputs (SA and SB), to the delayed versions of these syncs (DSA and DSB), to the terminal count of the

internal counter (TC), or to the one-shot strobe (OS). The sync to each circuit can also be set to be always

on or always off. Each circuit is given a three bit sync mode control which is defined as:

NOTE: the internal syncs are active high. The SA and SB inputs have been inverted to be the active

high syncs SA and SB.

The suggested default setting for SYNC_REG0 is to sync everything to SA, value = 0249 (HEX).

ADDRESS 1:

SYNC_REG0

BIT

TYPE

NAME

DESCRIPTION

0-2 (LSBs)

R/W

COUNT_SYNC

The counter sync selection

3-5

R/W

OUTPUT_SYNC

The selected sync is inverted and output on the SO pin.

6-8

R/W

OFFSET_SYNC

The symbol offset sync.

9-11

R/W

SNAP_SYNC

The snapshot memory can be triggered by this sync.

12

R/W

USE_HSO

Use the HSO sync (See Section 2.4) for the SB sync.

13

R/W

USE_CLK_EN

The clock enables CKENA and CKENB are ignored

when this bit is low.

14,15

R/W

POWER_DOWN

These bits control the power down and keep alive circuit.

POWER_DOWN

MODE

0

Keep alive

1

Power down

2

Off

3

Test

The USE_CLK_EN and POWER_DOWN bits initialize to zero upon power up. This puts the chip in

the keep alive mode to prevent a current surge if there is no clock provided. See Section 2.13 for details.

Table 3: SYNC MODES

MODE

SYNC DESCRIPTION

0

“0” (never asserted)

1SA

2

SB (or HSO if USE_HSO is set)

3

DSA

4

DSB (or HSO if USE_HSO is set)

5TC

6OS

7

“1” (always asserted)