GRAYCHIP, INC.

- 9 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

24 for initial acquisition and 31 for final tracking. The values of A and B are double buffered so that the loop

bandwidth can be changed synchronous to an external sync signal.

Initial acquisition can be greatly aided by presetting the PLL to an estimated frequency offset. This

is done by loading the frequency register with the estimated frequency.

the frequency register to the desired tuning frequency. The 32 bit frequency word is set to the desired

frequency using the formula:

, where “Frequency” is the desired

frequency and “Clock Rate” is the chip’s clock rate. The frequency register is double buffered so that

frequency changes can be made synchronous to external sync signals.

The upper 16 bits of the current phase increment is monitored by the phase increment register. The

register tracks the current phase increment when the “hold” control is low and holds the last value when

“hold” is high. The user may wish to monitor the phase increment in order to reinitialize the PLL after a loss

of signal, or to determine when carrier lock has been achieved.

2.9

NCO

The PLL circuit generates a phase increment word which is used by the NCO to generate a

sine/cosine sequence at the desired tuning frequency. The NCO circuit accumulates the phase and uses

the upper 13 bits of the 32 bit accumulator to lookup 12 bit sines and cosines. A block diagram of the NCO

circuit is shown in Figure 8.

Figure 8. NCO CIRCUIT

up the BCOS and BSIN values. This generates the proper “odd time” sine/cosine values needed in the high

1. The high speed mode is the double rate real input mode, see Section 2.4

FREQ

Frequency

Clock Rate

-----------------------------2

32

=

32 BIT PHASE ACCUMULATOR

NCO Sync

PHASE

INCREMENT

DIVIDE BY 2

Clear

Dither

Sync

High Speed

Mode

TRIG

TABLE

ACOS

ASIN

13 Bits

17 Bits

17 Bits

12 Bits

12 Bits

TRIG

TABLE

BCOS

BSIN

13 Bits

12 Bits

12 Bits

Negate Sine

CIN