GC3021 datasheet(15/37 Pages) TI1

15 / 37 page

GRAYCHIP, INC.

- 13 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

3.1

PIN DESCRIPTIONS

SIGNAL

DESCRIPTION

I[0:11]

IN-PHASE INPUT DATA.

Active high

The 12 bit two’s complement input samples for the I half of the

complex input. New samples are clocked into the chip on the rising

edge of the clock. In the high speed mode this is the positive rail

of the differential PECL inputs.

Q[0:11]

QUADRATURE INPUT DATA.

Active high

The 12 bit two’s complement input samples for the Q-half of the

complex input. New samples are clocked into the chip on the rising

edge of the clock. In the high speed mode this is the negative rail

of the differential PECL inputs

CIN

NCO CARRY INPUT.

Active high

The carry input to the phase accumulator in the NCO. The CIN

input can be used to increase the tuning resolution of the NCO.

This signal is clocked into the chip on the rising edge of the clock.

The CIN input is cleared by the chip during diagnostics.

EIN

PHASE ERROR INPUT.

Active high

This input can be used as the error input into the PLL circuit. This

signal is clocked into the chip on the rising edge of the clock.

SA,SB

SYNC INPUTS.

Active low

The sync inputs to the chip. All timers, accumulators, and control

counters are, or can be, synchronized to these syncs. The syncs

are clocked into the chip on the rising edge of the clock.

SNAPSHOT SYNC.

Active low

The snapshot sync is provided to synchronously start the data

snapshot. This signal is clocked into the chip on the rising edge of

the clock.

CLOCK INPUT.

Active high

The clock input to the chip. The I, Q, SA, SB, SN, CKENA,

CKENB, EIN and CIN signals are clocked into the chip on the

rising edge of this clock. The YA, YB, YC, YD, EOUT and SO

signals are clocked out on the rising edge of this clock.

CKENA, CKENB

CLOCK ENABLE INPUTS.

Active low

The clock enable inputs to the chip. These signals are gated with

CK to generate the chip’s internal clock. CKENA and CKENB are

clocked into the chip on the rising edge of CK and will enable or

disable the following clock edge. A low level on both CKENA and

CKENB enables the clock edge.

YA[0:11]

YA OUTPUT DATA.

Active high

YB[0:11]

YB OUTPUT DATA.

Active high

YC[0:11]

YC OUTPUT DATA.

Active high

YD[0:11]

YD OUTPUT DATA.

Active high

These pins output the complex mixer or symbol outputs. The bits

are clocked out on the rising edge of the clock.

AOE,BOE,COE,DOE

OUTPUT ENABLES.

Active low

The YA, YB, YC and YD output pins are put into a high impedance

state when these pins are high. AOE controls the YA output pins.

BOE controls the YB output pins. COE controls the YC output

pins. DOE controls the YD output pins.

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