GC3021 datasheet(25/37 Pages) TI1

25 / 37 page

GRAYCHIP, INC.

- 23 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

PARAMETER

MIN

TYP

MAX

UNITS

FCK

Clock frequency1

VCC= 5v

0.1

MHz

3.3v

0.1

tCKL

Clock low period (Below VIL)VCC=5v

3.3V

tCKH

Clock high period (Above VIH)VCC=5v

3.3v

tSU

Data setup (I,Q,SA, SB, SN, CKENA, or CKENB) before CK goes high

VCC=5v

3.3v

tHD

Data hold time after CK goes high

tDLY

Data output delay (Y, EOUT, or SO) from CK2

VCC=5v

3.3v

tDZ

Data to tristate delay (Y to hiZ from OE)

VCC=5v

3.3v

tZD

Tristate to data output delay (Y valid from OE)

VCC=5v

3.3v

tCSU

Control setup before CS goes low

(A, R/W during read, and A, R/W, C during write)

tCHD

Control hold after CS goes high

(A, R/W during read, and A, R/W, C during write)

tCSPW

Control strobe pulse width (Write operation)

tCDLY

Control output delay to C after CS goes low3

(Read operation)

tCZ

Control tristate delay after CS goes high

ICCQ

Quiescent supply current (VIN=0 or VCC, FCK=100Hz)

200

µA

ICC

Supply current (FCK=50 MHz, VCC=5.0V)

150

1. The chip may not operate properly at clock frequencies below MIN and above MAX,

2. Capacitive output load is 20 pf. Delays are measured from the rising edge of the clock to the output level rising above VIH or falling

below VIL.

3. Capacitive output load is 80 pf.

ICC (MAX)

VCC

------------



 FCK

50M

-----------





150 mA

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