GRAYCHIP, INC.

- 8 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

The rounded bits are passed to the unsigned magnitude circuit where, if Qmap is enabled, they are

converted from 7 bit 2’s complement signed numbers to 6 bit unsigned numbers. The conversion is

performed using 2’s complement negation unless the invert control is set. If the invert control is set, then the

negation is performed by inverting the data bits (i.e., a 1’s complement negation is used).

If Qmap is enabled the circuit outputs the 6 bit magnitude and the sign bit. If Qmap is turned off the

circuit outputs the 6 bit signed number from the round circuit.

The Qmap mode is used to map the I, Q complex pair into one quadrant for looking up the phase

error. This is possible when the signal’s constellation pattern has quadrant symmetry. If the pattern does

not exhibit symmetry, then the quadrant map mode should not be used.

The 6 bit I and Q values are used to lookup the phase error in a 4096 by 1 bit memory. In the Qmap

mode the phase error is inverted as necessary to map it back into the proper quadrant.

The memory is implemented using a 256 word by 16 bit RAM as shown in Figure 6. The RAM is

loaded as 256 sixteen bit words mapped to addresses 256 to 511 of the control interface. The RAM is a

write only memory.

The phase error is passed to the phase lock loop (PLL) circuit. The phase error is also output on

the EOUT pin of the chip for external use.

2.8

PHASE LOCK LOOP

The phase error drives the PLL circuit shown in Figure 7.

Figure 7. PLL CIRCUIT

The phase error can either come from an input pad or from the phase error RAM. The error is

The tracking bandwidth and damping of the of the phase lock loop filter are set using the constants

A and B. The filter will be critically damped when A is approximately one-half of B. When critically damped

the tracking bandwidth and residual phase jitter of the loop are set by B. A small value for B results in a wide

bandwidth with lots of jitter, but fast acquisition. A large value of B narrows the bandwidth and reduces the

residual jitter, but increases the initial acquisition time. Values of B between 24 and 31 are suggested. Use

Error From

Phase RAM

External

FREQUENCY

32 BIT ERROR ACCUMULATOR

(32 BITS)

PLL Sync

Error Input

Phase

32 BITS

External

MUX

32 BITS

Increment

To NCO

To

Control

Interface

phase_hold