GC3021 datasheet(17/37 Pages) TI1

17 / 37 page

GRAYCHIP, INC.

- 15 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

4.0

CONTROL REGISTERS

The chip is configured and controlled through the use of 14 sixteen bit control registers. These

registers are accessed for reading or writing using the control bus pins (CS, R/W, A[0:8], and C[0:15])

described in the previous section. The register names and their addresses are:

ADDRESS

NAME

ADDRESS

NAME

MODE_REG

OUTPUT_REGA

SYNC_REG0

OUTPUT_REGB

SYNC_REG1

OUTPUT_REGC

DELAY_REG

OUTPUT_REGD

COUNTER_REG0

SNAP_REG

PLL_REG

PHASE_REG

FREQ_REG0

ONE_SHOT

FREQ_REG1

TEST_OUT

DC_I_IN

DC_Q_IN

DC_I_OUT

DC_Q_OUT

20 to 255

unused

256 to 511

Snapshot memory (read only)

256 to 511

Phase Error memory (write only)

The DC offset registers contain two’s complement values. Only the 12 LSBs are used.

The following sections describe each of these registers. The type of each register bit is either R or

R/W indicating whether the bit is read only or read/write. All bits are active high.

Suggested default settings for using the chip in carrier removal applications is given for each

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