GC3021 datasheet(20/37 Pages) TI1

20 / 37 page

GRAYCHIP, INC.

- 18 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

The suggested default value for SYNC_REG1 is 7DF7 (HEX) which is to always sync AB_SYNC,

FREQ_SYNC and DITHER_SYNC (turns dithering off) and to sync PLL_SYNC and NCO_SYNC with the

oneshot strobe.

ADDRESS 2:

SYNC_REG1

BIT

TYPE

NAME

DESCRIPTION

0-2 (LSBs)

R/W

AB_SYNC

The PLL circuit accepts new A and B values when the

sync is asserted.

3-5

R/W

PLL_SYNC

The PLL accumulator is cleared by this sync.

6-8

R/W

FREQ_SYNC

The PLL accepts the new FREQ value from the FREQ

registers when this sync is asserted.

9-11

R/W

NCO_SYNC

The NCO accumulator is cleared by this sync.

12-14

R/W

DITHER_SYNC

The dither value circuit is cleared by this sync.

15 (MSB)

R/W

unused

4.3

DELAY CONTROL REGISTER

The DSA and DSB syncs are generated by delaying the SA and SB sync inputs by (2+DELAY)

clocks where DELAY ranges from 0 to 255. The suggested default is zero.

ADDRESS 3:

DELAY_REG

BIT

TYPE

NAME

DESCRIPTION

0-7 (LSBs)

R/W

DELAY_A

The DELAY value for DSA.

8-15 (MSBs) R/W

DELAY_B

The DELAY value for DSB.

4.4

COUNTER CONTROL REGISTER

The internal counter counts in cycles of 16*(COUNT+1) clocks by counting down from

(16*COUNT+15) to zero and starting over again. The counter emits a terminal count (TC) each time it

reaches zero. The suggested default is 00FF (HEX) which sets a counter cycle of 4096.

ADDRESS 4:

COUNT_REG

BIT

TYPE

NAME

DESCRIPTION

0-15

R/W

COUNT

The counter period is 16*(COUNT+1) clocks.

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