CXA2000 datasheet(42/48 Pages) SONY

42 / 48 page

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CXA2000Q

4. Notes on operation

Because the RGB signals and deflection signals output from the CXA2000Q are DC direct connected, the

board pattern must be designed consideration given to minimizing interference from around the power supply

and GND.

Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the by-

pass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also,

locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire

signal lines near this pin. Drive the Y, external Y/color difference and external RGB signals at a sufficiently low

impedance, as these signals are clamped when they are input using the capacitor connected to the input pin.

DC bias is applied to the chroma signal within the IC. Input the chroma signal with low impedance via an

external capacitor.

Use a resistor (such as a metal film resistor) with an error of less than 1% for the IREF pin.

Use a capacitor, such as an MPS (metalized polyester capacitor) with a small tan

δ for SAWOSC.

When using a line frequency FH of 15625Hz for the main clock (PAL-B, G, etc.), Murata's Ceralock

CSB500F63 is recommended. This will yield a free-run frequency in the neighborhood of 15625Hz.

CXA2000 Datasheet(PDF) 42 Page - Sony Corporation