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R262 Datasheet(PDF) 5 Page - ON Semiconductor

Part # R262
Description  Wideband Voice Capture and Noise Reduction Solution
PDF  28 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

R262 Datasheet(HTML) 5 Page - ON Semiconductor

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BelaSigna R262
http://onsemi.com
5
Table 2. ELECTRICAL CHARACTERISTICS (continued) (The typical parameters in Table 2 were measured at 20°C with a clean
3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified
for all process corners but not tested on every part.)
Parameter
Screened
Unit
Max
Typ
Min
Test Conditions / Notes
Symbol
DIRECT DIGITAL OUTPUT (available only through custom configuration)
Dynamic Range
DR
80
86
dB
l
Noise Floor
50
75
mV
l
LOW−SPEED A/D
Input voltage
Vin
0
2*VREG
V
Sampling frequency
For each LSAD channel
1.6
MCLK/28
4.8
kHz
Input impedance
Rin
1
MW
Offset error
Input at VREG
−10
10
LSB
Gain error
Input to VSSA or 2*VREG
−10
10
LSB
INL
INL
−4
4
LSB
DNL
DNL
−2
2
LSB
DIGITAL PADS (VDDO = 1.8 V)
Voltage level for Low input
VIL
−0.3
0.4
V
Voltage level for High input
VIH
1.30
1.98
V
Pull−up resistance
63
114
162
kW
Pull−down resistance
87
153
205
kW
Rise and Fall Time
20 pF load
2
3
5
ns
DIGITAL PADS (VDDO = 3.3 V)
Voltage level for Low input
VIL
−0.3
0.8
V
l
Voltage level for High input
VIH
1.8
3.6
V
l
Pull−up resistance
34
46
74
kW
l
Pull−down resistance
29
56
86
kW
l
Rise and Fall Time
20 pF load
1.0
1.5
2.0
ns
DIGITAL PADS (Common parameters)
Drive Strength
12
mA
ESD Immunity
HBM
Human Body Model
2
kV
MM
Machine Model
200
V
Latch−up Immunity
25°C, V < GNDO, V > VDDO
150
mA
CLOCKING CIRCUITRY
External clock frequency
EXT_CLK
With preset 6 selected on
CLOCK_SEL (Note 3)
26
MHz
Internal clock frequency
INT_CLK
With preset 7 selected on
CLOCK_SEL (Note 3)
Bypass Mode
5.2
MHz
With preset 7 selected on
CLOCK_SEL (Note 3)
Active Mode
48.2
MHz
Reference clock duty cycle
40
50
60
%
External Input clock jitter
Maximum allowed jitter on
EXT_CLK
10
ns
I2C INTERFACE
Maximum speed
400
kbps
3. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this
document and in the BelaSigna R262 Communications and Configuration Guide for more information on custom mode usage.



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