BelaSigna R262

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2

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Unit

Power Supply (Applies on VBAT, VBATRCVR and VDDO for “Max” and for

VSSA, VSSRCVR and VSSD for “Min”) (Note 1)

−0.3

4.0

V

Digital input pin voltage

VSSD − 0.3 V

VDDO + 0.3 V

V

Operating temperature range

−40

85

°C

Storage temperature range

−40

85

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Time limit at maximum voltage must be less than 100 ms.

NOTE: Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

This device series incorporates ESD protection and is tested by the following methods:

− ESD Human Body Model (HBM) tested per AEC−Q100−002 (EIA/JESD22−A114)

− ESD Machine Model (MM) tested per AEC−Q100−003 (EIA/JESD22−A115)

This device series incorporates latch−up immunity and is tested in accordance with JESD78.

Electrical Performance Specifications

3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified

for all process corners but not tested on every part.)

Parameter

Symbol

Test Conditions / Notes

Min

Typ

Max

Unit

Screened

OVERALL

Supply voltage

VBAT

1.65

3.3

3.63

V

Maximum rise time

Between 0 V and 1.8 V

10

ms

Average current consumption

Active mode, VBAT = 3.3 V,

EXT_CLK = 2.048 MHz

16.0

16.5

17.0

mA

Bypass mode, VBAT = 3.3 V,

EXT_CLK = 2.048 MHz

16.0

16.5

17.0

mA

Bypass mode, VBAT = 3.3 V,

Internal clock

2.7

2.8

2.9

mA

Sleep mode, VBAT = 3.3 V

39

40

mA

Peak active current

VBAT = 3.63 V

19

21

mA

VREG (1 mF External Capacitor)

Output voltage

VREG

Without load, or with micro-

phone attached (0 to 200 mA)

0.95

1.00

1.05

V

l

PSRR

@ 1 kHz

40

dB

Load regulation

@ 2 mA

5

20

mV/mA

Load current

2

mA

Line regulation

−1

5

mV/V

VDDA (1 mF External Capacitor on VDDA + 100 nF External Capacitor on CAP0/CAP1)

Output voltage

VDDA

Unloaded with VREG = 1 V

1.8

2.0

2.1

V

l

PSRR

@ 1 kHz

45

dB

Load regulation

@ 1 mA

100

140

mV/mA

Load current

1

mA

Line regulation

2

mV/V

VDDD (1 mF External Capacitor)

Output voltage

VDDD

1.62

1.70

1.98

V

l