R262 datasheet(22/28 Pages) ONSEMI

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BelaSigna R262

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more information on the supported DMIC clock

frequencies.

The DMIC output can be configured to carry a mono or

stereo signal. In fact both left and right signals can be

configured to either contain output stage channel 0 or output

stage channel 1. Also, both left and right can be configured

to be muted independently (driving a ‘0’ all the time).

Figure 12 shows the timing of the DMIC output data

relative to the incoming DMIC_CLK signal. See Table 2 for

electrical specifications of the timing parameters.

Figure 12. DMIC Timing Diagram

DMIC_CLK

DMIC_DATA

Left

Data 0

Right

Data 2

DMIC_

HOLD

DMIC_

HOLD

DMIC_

SETUP

DMIC_

SETUP

Right

Data 0

Left

Data 1

Right

Data 1

The application pre−configures the DMIC interface based

on the CHAN_SEL pin; when in a stereo configuration, it

always outputs a stereo signal with Channel 0 as the right

signal, and Channel 1 as the left signal. When in a mono

configuration, both the right and left signals will contain the

data processed on Channel 0, unless the SWAP_CHAN pin

was used to toggle the channels, in which case the DMIC

output would see the Channel 1 output on both left and right

signals.

When the DMIC interface is not required, the analog

outputs can be used for interfacing at line−level or other signal

levels, e.g. microphone levels for an external system such as

an analog baseband chipset which expects low−level

signals.

There are two configurable aspects of the analog output

stage – the selection of stereo (two single−ended outputs) or

mono (one differential output) and the output attenuation.

When a stereo single−ended option is selected, each channel

is filtered to generate an analog signal which is then scaled

by a configurable output attenuator (OA in Figure 12). In

mono differential mode, Channel 1 is replaced by an

inverted version of Channel 0 such that the two output pins

contain a differential signal for Channel 0. In this latter case,

both output attenuators are used, so it is mandatory to ensure

that they have the same attenuation settings. The default

attenuation value is 0 dB for both channels. This can be

configured using I2C commands.

The 26−ball WLCSP package option doesn’t provide

access to A_OUT0. Consequently, only A_OUT1 is available

as an analog output. When using this package, careful design

consideration must be taken to ensure that the desired signal

is available on Channel 1, i.e. on the A_OUT1 pin.

A third output stage option is available on BelaSigna

R262; using the Class−D output driver which can drive an

output transducer without the need for a separate power

amplifier. The output driver can also be configured for single

ended stereo or differential mono through the same I2C

commands as described for the analog outputs. The output

driver is disabled by the default application in ROM.

For optimal audio performance it is important to note that

the VBATRCVR power supply must be connected

differently, depending on whether the output driver or the

analog outputs are being used:

• When using the analog outputs, VBATRCVR must be

connected to VDDA on the application PCB

• When using the output driver, VBATRCVR must be

connected to VBAT on the application PCB and must

be decoupled with an external capacitor

When interfacing BelaSigna R262 with other processors

like codecs or baseband chipsets, it is not recommended to

use the Class−D output driver, but rather the analog outputs.

Clock Generation Circuitry

BelaSigna R262 is equipped with a fully configurable and

flexible clocking system, which allows for many clocking

configurations for various use cases. Computing

applications typically require the use of a DMIC interface,

which imposes constraints on the BelaSigna R262 clocking

system, such as it provides full synchronization between an

incoming DMIC clock and the DMIC data that the chip will

produce. The clock frequencies that these systems usually

operate with are in the range of 2.048 to 3.072 MHz. Mobile

phone applications would typically use much higher clock

frequencies; historically, baseband systems have been using

13 MHz or 26 MHz, or even 19.2 MHz or 38.4 MHz.

To support such a wide variety of clocking scenarios,

BelaSigna R262 has a phase locked loop (PLL) integrated as

one of the components of its clock generation circuitry.

Clock frequencies can be selected using the CLOCK_SEL

pin, as discussed previously. BelaSigna R262 can also

operate on its internal RC oscillator, offering the same

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