R262 datasheet(19/28 Pages) ONSEMI

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BelaSigna R262

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The use of a resistive divider as shown in Figure 8 allows

the application to select the appropriate combination of

clock, output stage and algorithm mode. The LSAD is using

a voltage range between 0 and 1 V. The actual voltage levels

that need to be guaranteed by the application circuitry are

also mentioned in Figure 8. The figure proposes actual

resistor values to reach the eight different presets.

Figure 8. Resistive Dividers for LSAD Preset

Selection

LSAD Pin

VREG

Preset

Voltage Range

0−2

10 kW

−

0.65 − 1.00 V

75 kW

100 kW

0.50 − 0.63 V

100 kW

75 kW

0.36 − 0.49 V

100 kW

39 kW

0.22 − 0.35 V

100 kW

16 kW

0.08 − 0.21 V

−

10 kW

0 − 0.07 V

The configuration is only read by the chip at boot time.

Consequently, if the voltage on any of the four LSAD inputs

changes during operation, it will only have an impact at the

next power cycle.

Channel Swapping

BelaSigna R262 has provisions to swap the two output

channels by using an external GPIO pin (SWAP_CHAN).

The two output channels of BelaSigna R262 can be swapped

whenever the digital signal on this pin transitions to low and

stays low for at least 200 ms, as shown in Figure 9. The actual

channel swapping can occur at any time during the 200 ms

low period of the signal. This control mechanism has built-in

button de-bouncing and will work with either a digital signal

driven high or low by a host controller, or with a control

signal provided by a mechanical button or switch.

Figure 9. SWAP_CHAN Timing Diagram

Channel State

SWAP_CHAN

Normal

Swapped

Normal

200 ms (min)

Sleep Control

As described in Table 8, there are two methods to enter and

exit from Sleep mode. Both of these methods are meant to

be used independently, i.e. methods of putting the system

into Sleep mode and waking it up from Sleep mode cannot

be mixed in the same system design.

The first method for Sleep mode control is via the I2C

interface. The Switch_Mode command can be used directly

to switch the system into and out of Sleep mode. If the

Switch_Mode command is used to put the chip into Sleep

mode, only another Switch_Mode command or a reset will

take the system out of Sleep mode. When waking up by I2C

commands, the following I2C operations have to be

performed by the master I2C to ensure proper wake−up:

1. Send a NOP command to wake up the I2C

interface. This command will not be interpreted by

BelaSigna R262, so the master will have to deal

with any I2C errors that result.

2. Send the Get_Status command in a while−type loop,

until a response from BelaSigna R262 is sent, and

that confirms that the application is in Standby Mode.

3. Send a Switch_Mode command to enter the desired

mode (Active or Bypass).

When the NOP command is sent and the chip wakes up,

the master has about one second to complete the above

procedure before the chip goes back to Sleep mode. This

mechanism was put in place to deal with I2C bus traffic that

would wake the chip up unintentionally (i.e. communications

between the master and another slave on the I2C bus).

The second mechanism for entering Sleep mode is

considered a fail safe mechanism to maintain a graceful

system shutdown in the event that the clock source suddenly

disappears. In this circumstance, the chip will enter sleep

mode to ensure proper shutdown. More information on this

can be found in the System Monitoring section.

R262 Datasheet(PDF) 19 Page - ON Semiconductor

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