R262 datasheet(9/28 Pages) ONSEMI

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BelaSigna R262

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Figure 3. Proposed Ground Plane Positioning (soldering footprint view)

567

Analog Ground Plane

Digital Ground Plane

F6 = VBAT

D6 = A_OUT0

E7 = A_OUT1

G7 = CAP0

F8 = CAP1

G9 = VBATRCVR

E9 = VSSRCVR

B6 = VDDD

C7 = DMIC_OUT

A7 = SPI_CLK

A7 = CLOCK_SEL

B8 = SPI_SERO

B8 = CHAN_SEL

A9 = SPI_CS

A9 = BOOT_SEL

C9 = SPI_SERI

C9 = ALPHA_SEL

F2 = RESERVED

G3 = VREG

E3 = VMIC

G1 = MIC0

E1 = MIC2

F4 = VSSA

D4 = NRESET

G5 = VDDA

E5 = AI1

C1 = I2C_SCL

C3 = I2C_SDA

C5 = SWAP_CHAN

B4 = VDDO

A5 = VSSD

A3 = EXT_CLK

A1 = DEBUG_RX

B2 = DEBUG_TX

The VSSD plane is used as the ground return for digital

circuits and should be placed under digital circuits. The

VSSA plane should be kept as noise−free as possible. It is

used as the ground return for analog circuits and it should

surround analog components and pins. It should not be

connected to or placed under any noisy circuits such as RF

chips, switching supplies or digital pads of BelaSigna R262

itself. Analog ground returns associated with the audio

output stage should connect back to the star point on separate

individual traces.

For details on which signals require special design

consideration, see Table 4 and Table 5.

In some designs, space constraints may make separate

ground planes impractical. In this case a star configuration

strategy should be used. Each analog ground return should

connect to the star point with separate traces.

Internal Power Supplies

Power management circuitry in BelaSigna R262

generates separate digital (VDDD) and analog (VREG,

VDDA) regulated supplies. Each supply requires an

external decoupling capacitor, even if the supply is not used

externally. Decoupling capacitors should be placed as close

as possible to the power pads.

The digital I/O levels are defined by a separate power

supply pin on BelaSigna R262 (VDDO). This pin must be

externally connected by the application PCB, usually to

VBAT.

Further details on these critical signals are provided in

Table 4. Non−critical signals are outlined in Table 5. More

information on the power supply architecture can be found

in the Power Supply Unit section.

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