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WM8351 Datasheet(PDF) 211 Page - Wolfson Microelectronics plc |
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WM8351 Datasheet(HTML) 211 Page - Wolfson Microelectronics plc |
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211 / 330 page  Production Data WM8351 w PD, April 2012, Rev 4.5 211 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R38 (26h) GPIO Interrupt Status Mask 0 0 0 IM_GP12_E INT (s) IM_GP11_E INT (s) IM_GP10_E INT (s) IM_GP9_EI NT (s) IM_GP8_EI NT (s) IM_GP7_EI NT (s) IM_GP6_EI NT (s) IM_GP5_EI NT (s) IM_GP4_EI NT (s) IM_GP3_EI NT (s) IM_GP2_EI NT (s) IM_GP1_EI NT (s) IM_GP0_EI NT (s) 0000h R39 (27h) Comparator Interrupt Status Mask IM_EXT_US B_FB_EINT (s) IM_EXT_W ALL_FB_EI NT (s) IM_EXT_BA TT_FB_EIN T (s) 0 IM_CODEC _JCK_DET_ L_EINT (s) IM_CODEC _JCK_DET_ R_EINT (s) IM_CODEC _MICSCD_ EINT (s) IM_CODEC _MICD_EIN T (s) 0 IM_WKUP_ OFF_STAT E_EINT (s) IM_WKUP_ HIB_STATE _EINT (s) IM_WKUP_ CONV_FAU LT_EINT (s) IM_WKUP_ WDOG_RS T_EINT (s) IM_WKUP_ GP_PWR_ ON_EINT (s) IM_WKUP_ ONKEY_EI NT (s) IM_WKUP_ GP_WAKE UP_EINT (s) 0000h R40 (28h) Clock Control 1 TOCLK_EN A TOCLK_RA TE 0 0 MCLK_SEL 0 0 MCLK_DIV BCLK_DIV[3:0] 0 OPCLK_DIV[2:0] 0040h R41 (29h) Clock Control 2 LRC_ADC_ SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCLK_DIR 0000h R42 (2Ah) FLL Control 1 FLL_ENA FLL_OSC_ ENA 1 1 1 FLL_OUTDIV[2:0] FLL_RSP_RATE[3:0] 0 FLL_RATE[2:0] 3A00h R43 (2Bh) FLL Control 2 FLL_RATIO[4:0] 0 FLL_N[9:0] 7086h R44 (2Ch) FLL Control 3 FLL_K[15:0] C226h R45 (2Dh) FLL Control 4 0 0 0 0 0 0 0 0 FLL_REF_F REQ 0 FLL_FRAC 0 0 0 FLL_CLK_SRC[1:0] 0000h R48 (30h) DAC Control 0 0 DAC_MON O AIF_LRCLK RATE 0 0 0 0 0 0 DEEMP[1:0] DAC_SDMC LK_RATE 0 DACL_DATI NV DACR_DAT INV 0000h R50 (32h) DAC Digital Volume L DACL_ENA 0 0 0 0 0 0 DAC_VU DACL_VOL[7:0] 00C0h R51 (33h) DAC Digital Volume R DACR_ENA 0 0 0 0 0 0 DAC_VU DACR_VOL[7:0] 00C0h R53 (35h) DAC LR Rate 0 0 0 0 DACLRC_E NA DACLRC_RATE[10:0] 0040h R54 (36h) DAC Clock Control 0 0 0 0 0 0 0 0 0 0 0 DACCLK_P OL 0 DAC_CLKDIV[2:0] 0000h R58 (3Ah) DAC Mute 0 DAC_MUTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000h R59 (3Bh) DAC Mute Volume 0 DAC_MUTE MODE DAC_MUTE RATE DAC_SB_FI LT 0 0 0 0 0 0 0 0 0 0 0 0 0000h R60 (3Ch) DAC Side 0 0 ADC_TO_DACL[1:0] ADC_TO_DACR[1:0] 0 0 0 0 0 0 0 0 0 0 0000h R64 (40h) ADC Control ADC_HPF_ ENA 0 0 0 0 0 ADC_HPF_CUT[1:0] 0 0 0 0 0 0 ADCL_DATI NV ADCR_DAT INV 8000h R66 (42h) ADC Digital Volume L ADCL_ENA 0 0 0 0 0 0 ADC_VU ADCL_VOL[7:0] 00C0h R67 (43h) ADC Digital Volume R ADCR_ENA 0 0 0 0 0 0 ADC_VU ADCR_VOL[7:0] 00C0h R68 (44h) ADC Divider 0 0 0 0 ADCL_DAC_SVOL[3:0] ADCR_DAC_SVOL[3:0] ADCCLK_P OL ADC_CLKDIV[2:0] 0000h R70 (46h) ADC LR Rate 0 0 0 0 ADCLRC_E NA ADCLRC_RATE[10:0] 0040h R72 (48h) Input Control 0 0 0 0 0 IN2R_ENA IN1RN_ENA IN1RP_ENA 0 0 0 0 0 IN2L_ENA IN1LN_ENA IN1LP_ENA 0303h R73 (49h) IN3 Input Control IN3R_ENA IN3R_SHO RT 0 0 0 0 0 0 IN3L_ENA IN3L_SHOR T 0 0 0 0 0 0 0000h |
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